PIC32MX460F512L-80V/BG Microchip Technology, PIC32MX460F512L-80V/BG Datasheet - Page 203

• Manufacturer Part Number: PIC32MX460F512L-80V/BG
• Description: 512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x10x1.20mm
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80V/BG

• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-121
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

APPENDIX A: REVISION HISTORY
Revision E (July 2008)
• Updated the PIC32MX340F128H features in
TABLE A-1:
© 2011 Microchip Technology Inc.
“High-Performance, General
Purpose and USB 32-bit Flash
Microcontrollers”
Section 1.0 “Device Overview”
Section 2.0 “Guidelines for
Getting Started with 32-bit
Microcontrollers”
Section 4.0 “Memory
Organization”
Section 7.0 “Interrupt
Controller”
Section 12.0 “I/O Ports”
Table 1 to include 4 programmable DMA
channels.
Section Name
MAJOR SECTION UPDATES
Added a “Packages” column to Table 1 and Table 2.
Corrected all pin diagrams to update the following pin names.
• Changed PGC1/EMUC1 to PGEC1
• Changed PGD1/EMUD1 to PGED1
• Changed PGC2/EMUC2 to PGEC2
• Changed PGD2/EMUD2 to PGED2
Shaded appropriate pins in each diagram to indicate which pins are 5V tolerant.
Added 64-Lead QFN package pin diagrams, one for General Purpose and one
for USB.
Reconstructed Figure 1-1 to include Timers, ADC and RTCC in the block
diagram.
Added a new section to the data sheet that provides the following information:
• Basic Connection Requirements
• Capacitors
• Master Clear Pin
• ICSP™ Pins
• External Oscillator Pins
• Configuration of Analog and Digital Pins
• Unused I/Os
Updated the memory maps, Figure 4-1 through Figure 4-6.
All summary peripheral register maps were relocated to Section 4.0 “Memory
Organization”.
Removed the “Address” column from Table 7-1.
Added a second paragraph in Section 12.1.3 “Analog Inputs” to clarify that all
pins that share ANx functions are analog by default, because the AD1PCFG
register has a default value of 0x0000.
Revision F (June 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
• Changed all instances of V
• Deleted registers in most sections, refer to the
The other changes are referenced by their respective
section in the following table.
OSCO to OSC2
V
related section of the “PIC32 Family Reference
Manual” (DS61132).
Update Description
DDCORE
PIC32MX3XX/4XX
/V
CAP
to V
CAP
/V
DDCORE
DDCORE
DS61143H-page 203
and