MM912H634CV1AER2 Freescale Semiconductor, MM912H634CV1AER2 Datasheet - Page 242

• Manufacturer Part Number: MM912H634CV1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.38.3.2
This section describes all the S12CPMU registers and their individual bits.
Address order is as listed in
4.38.3.2.1
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency range.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct PLL operation the
VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK frequency as shown in
VCOFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability).
Freescale Semiconductor
Address
0x0034
0x02FA
0x02FB
0x02FC
0x02F6
0x02F7
0x02F8
0x02F9
{
Reset
W
R
If PLL has locked (LOCK=1)
RESERVEDC
RESERVEDC
CPMUPROT
RESERVED
PMUTEST3
PMUTEST2
CPMUOSC
IRCTRIMH
IRCTRIML
CPMU
CPMU
Name
Register Descriptions
7
0
S12CPMU Synthesizer Register (CPMUSYNR)
Writing to this register clears the LOCK and UPOSC status bits.
f
exceed the specified maximum.
VCOFRQ[1:0]
VCO
must be within the specified VCO frequency lock range. Bus frequency f
W
W
W
W
W
W
W
R
R
R
R
R
R
R
Figure
0
6
1
OSCE
Bit 7
LVRT
Table 338. S12CPMU Synthesizer Register (CPMUSYNR)
0
0
0
337.
0
ernal_en
OSCBW
Table 337. CPMU Register Summary
vdd_ext
MM912_634 Advance Information, Rev. 4.0
5
0
= Unimplemented or Reserved
6
0
0
0
f VCO
TCTRIM[4:0]
0
OSCPINS_
REGFT2
0
LVRS
=
EN
5
0
0
NOTE
NOTE
4
1
2

f REF
REGFT1
0
LVRFS

IRCTRIM[7:0]
4
0
0
0

SYNDIV
3
1
SYNDIV[5:0]
REGFT0
0
LVRXS
3
0
0
0
+
1

2
1
OSCFILT[4:0]
0
REGT2
2
0
0
0
0
BUS
must not
Table
0
1
1
REGT1
1
0
0
0
339. Setting the
IRCTRIM[9:8]
0
0
RCEXA
REGT0
PROT
Bit 0
0
1
0
242