MCP795W10-I/SL Microchip Technology, MCP795W10-I/SL Datasheet - Page 36

• Manufacturer Part Number: MCP795W10-I/SL
• Description: SPI GPP RTCC, 1Kb EE, 64B SRAM, WD Timer, Event Detect, ID 14 SOIC .150in TUBE
• Manufacturer: Microchip Technology

MCP795WXX/MCP795BXX
9.1.10
The following protection has been implemented to pre-
vent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A Write Enable instruction must be issued to set
• After a byte write, page write, unique ID write, or
FIGURE 9-7:
9.1.12
The Clear Ram instruction is a 2-byte command that
will reset the internal SRAM to the known value. Using
this command, all locations in the SRAM are set to 00h
and the data value contained in the second byte of the
command is ignored.
FIGURE 9-8:
DS22280B-page 36
the write enable latch
STATUS register write, the write enable latch is
reset
DATA PROTECTION
CLEAR RAM INSTRUCTION
SCK
CS
SO
SI
CLRWDT
CLRRAM
SCK
0
CS
0
SO
SI
1
1
0
2
Instruction
1
3
0
0
0
4
1
1
1
5
0
Preliminary
6
High-Impedance
0
2
0
7
A7
0
3
8
6
• CS must be set high after the proper number of
• Access to the array during an internal EEPROM
• Block protect bits are ignored for UID writes
9.1.11
The Clear Watchdog command resets the internal
Watchdog Timer.
9 10 11 12 13 14 15
0
High-Impedance
clock cycles to start an internal write cycle
write cycle is ignored and programming is contin-
ued
4
5
1
4
Data
5
3
CLEAR WATCHDOG INSTRUCTION
0
6
2
 2011-2012 Microchip Technology Inc.
0
1 A0
7