NLXT905PE.C2 Cortina Systems Inc, NLXT905PE.C2 Datasheet - Page 14

• Manufacturer Part Number: NLXT905PE.C2
• Manufacturer: Cortina Systems Inc

Specifications of NLXT905PE.C2

• Number Of Receivers: 1
• Data Rate: 10Mbps
• Operating Supply Voltage (typ): 5V
• Package Type: PLCC
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 28
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Not Compliant

LXT905 Transceiver
Datasheet
249271, Revision 5.1
5 November 2007
2.9
2.9.1
2.9.2
Table 3
2.10
Cortina Systems
Loopback Functions
Internal Loopback
The LXT905 Transceiver provides a standard loopback mode, as specified in the IEEE
specification for the twisted-pair port. It also provides a forced internal loopback mode.
Loopback mode operates in conjunction with the transmit function. The LXT905
Transceiver internally loops back data that the MAC transmits, from the TXD pin, through
the Manchester encoder/decoder, to the RXD pin, and returning to the MAC.
A data collision disables standard loopback mode, clearing the RXD circuit for the TPI
data. Link fail, jabber, and full-duplex states also disable standard loopback. Loopback is
always enabled during forced internal loopback mode.
External Loopback/Full Duplex
The LXT905 Transceiver also provides an external loopback test mode for system-level
testing. When both LEDC/FDE and LBK are Low, the LXT905 Transceiver enables
external loopback and full-duplex mode, and disables internal loopback circuits, SQE, and
collision detection. Refer to
Loopback Modes
Link Integrity Test Function
Figure 7
integrity test determines the status of the receive side twisted-pair cable. Link integrity
testing is enabled when LI is tied High. When enabled, the receiver recognizes link
integrity pulses that transmit in the absence of receive traffic. If the LXT905 Transceiver
does not detect any serial data stream or link integrity pulses within 50~150 ms, the chip
enters a link fail state and disables the transmit and normal loopback functions. The
LXT905 Transceiver ignores any link integrity pulse with interval less than 2~7 ms. The
LXT905 remains in the link fail state until it detects either a serial data packet, or two or
more link integrity pulses.
®
High
High
LBK
Low
Low
Pin Settings
LXT905 Universal 10BASE-T Transceiver with 3.3 V Support
LEDC/
High
High
FDE
Low
Low
is a state diagram of the LXT905 Transceiver link integrity test function. The link
Disable internal loopback.
Enable external loopback test mode and full-duplex mode.
Standard loopback mode (default).
Internally loops back data that the MAC transmitted, and returns the data to the MAC, except
during collision.
A data collision disables standard loopback, clearing RXD for data on the twisted-pair port.
Not Used.
Forced internal loopback.
Loops-back transmit data on the receive data bus, and ignores the twisted-pair port.
Table 3
for a summary of loopback and duplex modes.
Mode Description
2.9 Loopback Functions
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