LAN8187I-JT SMSC, LAN8187I-JT Datasheet - Page 45

• Manufacturer Part Number: LAN8187I-JT
• Description: TXRX ETHERNET 10/100 ESD PROT
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8187I-JT

• Protocol: Ethernet
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: Q4223799

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR
Datasheet
SMSC LAN8187/LAN8187i
ADDRESS
ADDRESS
ADDRESS
16.15:10
17.15:14
6.15:5
16.9:6
16.5:0
17.8:7
17.13
17.12
17.10
17.11
17.9
6.4
6.3
6.2
6.1
6.0
Link Partner Auto-
Parallel Detection
Link Partner Next
Negotiation Able
Next Page Able
Silicon Revision
FARLOOPBACK
Page Received
EDPWRDOWN
LOWSQEN
Page Able
MDPREBP
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
NAME
NAME
NAME
Fault
Table 5.36 Register 6 - Auto Negotiation Expansion
Table 5.38 Register 17 - Mode Control/Status
Table 5.37 Register 16 - Silicon Revision
1 = fault detected by parallel detection logic
0 = no fault detected by parallel detection logic
1 = link partner has next page ability
0 = link partner does not have next page ability
1 = local device has next page ability
0 = local device does not have next page ability
1 = new page received
0 = new page not yet received
1 = link partner has auto-negotiation ability
0 = link partner does not have auto-negotiation ability
Four-bit silicon revision identifier.
Write as 0; ignore on read.
Enable the Energy Detect Power-Down mode:
0 = Energy Detect Power-Down is disabled
1 = Energy Detect Power-Down is enabled
Write as 0, ignore on read
The Low_Squelch signal is equal to LOWSQEN AND
EDPWRDOWN.
Low_Squelch = 1 implies a lower threshold
Low_Squelch = 0 implies a higher threshold
Management Data Preamble Bypass:
0 – detect SMI packets with Preamble
1 – detect SMI packets without preamble
Force the module to the FAR Loop Back mode, i.e. all
the received packets are sent back simultaneously (in
100Base-TX only). This bit is only active in RMII
mode. In this mode the user needs to supply a 50MHz
clock to the PHY. This mode works even if MII Isolate
(0.10) is set.
Write as 0, ignore on read.
DATASHEET
(more sensitive).
(less sensitive).
DESCRIPTION
DESCRIPTION
DESCRIPTION
45
TM
Technology
MODE
MODE
MODE
Revision 1.5 (01-10-08)
RO/
RO/
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
LH
LH
DEFAULT
DEFAULT
DEFAULT
0001
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0