LAN8187I-JT SMSC, LAN8187I-JT Datasheet - Page 15

• Manufacturer Part Number: LAN8187I-JT
• Description: TXRX ETHERNET 10/100 ESD PROT
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8187I-JT

• Protocol: Ethernet
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: Q4223799

High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Datasheet
SMSC LAN8187/LAN8187I
a.On nRST transition high, the PHY latches the state of the configuration pins in this table.
SIGNAL NAME
SIGNAL NAME
CH_SELECT
AMDIX_EN
GPO0/MII
REG_EN
MODE2
MODE1
MODE0
TEST1
TEST0
nRST
nINT
Table 3.4 Boot Strap Configuration Inputs
TYPE
TYPE
I/O
I/O
I
I
I
I
I
I
I
I
Table 3.5 General Signals
I
DATASHEET
PHY Operating Mode Bit 2: set the default MODE of the PHY.
See
the MODE options.
PHY Operating Mode Bit 1: set the default MODE of the PHY.
See
the MODE options.
PHY Operating Mode Bit 0: set the default MODE of the PHY.
See
the MODE options.
Test Mode Select 1: Must be left floating.
Test Mode Select 0: Must be left floating.
Regulator Enable: Internal +1.8V regulator enable:
VDDIO – Enables internal regulator.
VSS– Disables internal regulator.
HP Auto-MDIX Enable: Auto-MDIX mode enable.
+3.3V – Enables HP Auto-MDIX.
0V – Disables HP Auto-MDIX
Channel Select: With Auto-MDIX disabled above,
VDDIO – Enables HP Auto-MDIX.
0V – Disables HP Auto-MDIX
General Purpose Output 0 – General Purpose Output signal.
Driven by bits in registers 27 and 31.
MII – MII/RMII mode selection is latched on the rising edge of
the internal reset (nreset) based on the following strapping:
Float the GPO0 pin for MII mode or pull-high with an external
Pull-up resistor (see
Resistors,” on page
mode.
Note:
LAN Interrupt – Active Low output. Place a pull-up external
resistor (see
on page
Notes:
External Reset – input of the system reset. This signal is active
LOW.
This signal is mux’d with TX_ER/TXD4
See
page 30
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
Section 4.10, "(TX_ER/TXD4)/nINT Strapping," on
15
32) to VCC 3.3V.
See
page 26
for additional details on Strapping options.
Table 4.3, “Boot Strapping Configuration Resistors,”
Section 4.6.3, "MII vs. RMII Configuration," on
for more details.
32) to VDDIO to set the device in RMII
Table 4.3, “Boot Strapping Configuration
DESCRIPTION
DESCRIPTION
a
Revision 0.6 (02-24-06)
51, for
51, for
51, for