MT48LC16M16A2P-75 L Micron Technology Inc, MT48LC16M16A2P-75 L Datasheet - Page 60

• Manufacturer Part Number: MT48LC16M16A2P-75 L
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M16A2P-75 L

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

WRITE Operation
Figure 30: WRITE Burst
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Note:
WRITE bursts are initiated with a WRITE command, as shown in Figure 15 (page 34).
The starting column and bank addresses are provided with the WRITE command and
auto precharge is either enabled or disabled for that access. If auto precharge is ena-
bled, the row being accessed is precharged at the completion of the burst. For the
generic WRITE commands used in the following figures, auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered coincident with the
WRITE command. Subsequent data elements are registered on each successive positive
clock edge. Upon completion of a fixed-length burst, assuming no other commands
have been initiated, the DQ will remain at High-Z and any additional input data will be
ignored (see Figure 30 (page 60)). A continuous page burst continues until termina-
ted; at the end of the page, it wraps to column 0 and continues.
Data for any WRITE burst can be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst can be followed immediately by data for a WRITE
command. The new WRITE command can be issued on any clock following the previ-
ous WRITE command, and the data provided coincident with the new command ap-
plies to the new command (see Figure 31 (page 61)). Data n + 1 is either the last of a
burst of two or the last desired data element of a longer burst.
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule
associated with a prefetch architecture. A WRITE command can be initiated on any
clock cycle following a previous WRITE command. Full-speed random write accesses
within a page can be performed to the same bank, as shown in Figure 32 (page 62), or
each subsequent WRITE can be performed to a different bank.
Command
Address
1. BL = 2. DQM is LOW.
CLK
DQ
WRITE
Bank,
Col n
T0
D
IN
Transitioning data
NOP
T1
D
IN
60
NOP
T2
Don’t Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T3
NOP
256Mb: x4, x8, x16 SDRAM
© 1999 Micron Technology, Inc. All rights reserved.
WRITE Operation