UJA1023T/2R04 NXP Semiconductors, UJA1023T/2R04 Datasheet - Page 18

• Manufacturer Part Number: UJA1023T/2R04
• Manufacturer: NXP Semiconductors

Specifications of UJA1023T/2R04

• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 17.
UJA1023
Product data sheet
Data
byte
D0
D1
D2
D3
D4
D5
D6
D7
7
NAD7
0
1
0
CM0_7
CM1_7
TH2/TH1
LWM7
Second I/O configuration data block bit allocation
6
NAD6
0
0
1
CM0_6
CM1_6
TH2/TH1
LWM6
The second configuration data block (shown in
D3.6 = 1.
Table 18.
Byte
D0
D1
D2
D3
TH2/TH1
5
NAD5
0
1
LSLP
CM0_5
CM1_5
LWM5
Second I/O configuration data block bit description
Bit
7 to 0
7 to 0
7 to 0
7 and 6 -
5
4
3
2
1 and 0 SM[1:0]
All information provided in this document is subject to legal disclaimers.
Symbol
NAD[7:0]
PCI[7:0]
SID[7:0]
LSLP
TxDL
SMC
SMW
NAD4
0
1
TxDL
CM0_4
CM1_4
TH2/TH1
LWM4
4
Rev. 5 — 17 August 2010
3
NAD3
0
0
SMC
CM0_3
CM1_3
TH2/TH1
LWM3
Description
Slave node address (NAD). NAD values are in the range
from 1 to 127, while 0 and 128 to 255 are reserved for other
purposes. The slave node address is assigned with the
assign NAD command (see
Protocol control information.
Service identifier. As SlaveResp the RSID value will be
0xF4.
01 for the second configuration data block.
Limp home sleep mode. If LSLP = 1, the Limp home sleep
mode is enabled. In this case the Limp Home value (LH) is
automatically used as output value if the Sleep mode is
entered.
Transmit data length. Message PxResp contains two data
bytes if TxDL = 0 and four data bytes if TxDL = 1.
Switch matrix capture. If SMC = 1, the Switch matrix
capture mode is enabled.
Switch matrix wake-up. If SMW = 1, the switch matrix
wakes up upon changed input level.
Switch matrix enable
Unassigned pins can be used as I/O. It should be noted,
however, that for the unassigned pins, which are configured
in Capture mode, the captured edge value will not be
transferred.
00 = no switch matrix
01 = 4 × 2: P3 to P0 input and P5 and P4 strong pull
down
10 = 4 × 3: P3 to P0 input and P6 to P4 strong pull down
11 = 4 × 4: P3 to P0 input and P7 to P4 strong pull down
NAD2
CM0_2
CM1_2
TH2/TH1
2
1
1
SMW
LWM2
Table
17) is selected only if D3.7 = 0 and
NAD1
1
0
SM1
CM0_1
CM1_1
TH2/TH1
LWM1
1
Table
5).
0
NAD0
0
0
SM0
CM0_0
CM1_0
TH2/TH1
LWM0
UJA1023
© NXP B.V. 2010. All rights reserved.
LIN-I/O slave
NAD
40
00
00
00
Default
value (hex)
06
B4
00
18 of 49