AS1154-BSOT austriamicrosystems, AS1154-BSOT Datasheet
AS1154-BSOT
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AS1154-BSOT Summary of contents
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... Outputs conform to the ANSI TIA/EIA-644 LVDS standards. Flow- through pinout simplifies PC board layout and reduces crosstalk by separating the LVTTL/LVCMOS inputs and LVDS outputs. The AS1154 operates from a single +3.3V supply and is specified for operation from -40°C to +85°C. Figure 1. AS1154 - Block Diagram www ...
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... Inverting LVDS Driver Output Noninverting LVDS Driver Output 6 OUT2+ Noninverting LVDS Driver Output 7 OUT1+ Inverting LVDS Driver Output 8 OUT1- www.austriamicrosystems.com/Interfaces-LVDS/AS1154 VCC 1 8 OUT1- IN1 2 OUT1+ 7 AS1154 IN2 3 OUT2+ 6 GND 4 OUT2- 5 Description to GND with 0.1µF and 0.001µF ceramic capacitors. CC Revision 1. ...
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... Package Body Temperature Humidity non-condensing Moisture Sensitive Level 1. Depending on actual PCB layout and PCB used derating factor changes the total continuous power dissipation (P DERATE T =85ºC calculate P at 85º DERATE www.austriamicrosystems.com/Interfaces-LVDS/AS1154 Min Max Units -0.3 5.0 V -0.3 Vcc + 0.3 V -0.3 5.0 V Continuous +/- 4 ...
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... Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except V 2. Guaranteed by correlation data. 3. All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. www.austriamicrosystems.com/Interfaces-LVDS/AS1154 Typical values are +3.3V 100Ω ±1%, ( ...
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... MAX OL ≤ 1ns, t ≤ 1ns (0 to 100%). Transmitter output criteria: duty cycle = 45 to 55%, V 10. For optimum performance matched circuits should be used. www.austriamicrosystems.com/Interfaces-LVDS/AS1154 = -40°C to +85°C, (Typical values are Symbol Conditions Figure 20 on page 11 and t PHLD Figure 21 on page 12 Figure 20 on page 11 and ...
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... Figure 7. Differential Propagation Delay vs 1.05 1.03 t PHLD 1.01 0.99 0.97 t PLHD 0.95 3 3.1 3.2 3.3 3.4 Supply Voltage(V) www.austriamicrosystems.com/Interfaces-LVDS/AS1154 Figure 4. Transition Time vs. Temperature 350 300 250 200 150 100 50 0 3.5 3.6 -50 -30 Ambient Temperature(°C) Figure 6. Pulse Skew vs. Temperature 35 30 ...
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... V OUT+ 1.35 1.25 1.15 V OUT- 1.05 0.95 3 3.1 3.2 3.3 3.4 Supply Voltage (V) www.austriamicrosystems.com/Interfaces-LVDS/AS1154 Figure 10. Differential Output Voltage vs. Frequency 350 300 250 200 150 100 50 0 3.5 3 100 150 200 250 300 350 400 Figure 12. Offset Voltage vs. Frequency 1.35 1.3 1 ...
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... 10.6 10.2 9.8 9 3.1 3.2 3.3 3.4 Supply Voltage (V) Figure 17. Short Circuit Current vs 3.9 3.85 3.8 3.75 3.7 3.65 3.6 3 3.1 3.2 3.3 3.4 Supply Voltage(V) www.austriamicrosystems.com/Interfaces-LVDS/AS1154 Figure 16. I vs. Temperature 3.5 3.6 -50 -30 -10 Ambient Temperature(°C) Figure 18. I vs. Frequency 3.5 3.6 ...
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... With a typical 3.7mA output current, the AS1154 produces an output voltage of 370mV when driving a 100Ω load. Termination Because the AS1154 is a current-steering device, no output voltage will be generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. ...
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... CC Differential Traces Input trace characteristics can adversely affect the performance of the AS1154. Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor is also matched to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces near each other. ...
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... Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent coupling. Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. Figure 20. Driver Propagation Delay and Transition Time Waveforms 1.5V INx t PLHD OUTx- OUTx+ 20% t TLH www.austriamicrosystems.com/Interfaces-LVDS/AS1154 1.5V t PHLD 0 Differential 80% 80 ...
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... AS1154 Datasheet - Figure 21. Driver Propagation Delay and Transition Time Test Circuit Generator Figure 22. Driver V and V Test Circuit GND www.austriamicrosystems.com/Interfaces-LVDS/AS1154 50Ω OUTx INx OUTx- Revision 1.02 OUTx+ L OUTx ...
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... AS1154 Datasheet - Package Drawings and Markings Figure 23. 8-pin SOIC Marking Table 6. Packaging Code AYWWRZZ YY last two digits of the current year www.austriamicrosystems.com/Interfaces-LVDS/AS1154 WW R manufacturing week plant identifier Revision 1.02 ZZ free choice / traceability code ...
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... AS1154 Datasheet - Figure 24. 8-pin SOIC Package www.austriamicrosystems.com/Interfaces-LVDS/AS1154 Revision 1. ...
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... The devices are available as the standard products shown in Table 7. Table 7. Ordering Information Ordering Code Marking AS1154-BSOU AS1154 AS1154-BSOT AS1154 Note: All products are RoHS compliant. Buy our products or get free samples online at ICdirect: Technical Support is found at http://www.austriamicrosystems.com/Technical-Support For further information and requests, please contact us or find your local distributor at http://www ...
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... No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com/Interfaces-LVDS/AS1154 Revision 1. ...