MAX1997ETJ Maxim Integrated Products, MAX1997ETJ Datasheet - Page 19

• Manufacturer Part Number: MAX1997ETJ
• Description: LCD Drivers
• Manufacturer: Maxim Integrated Products

Specifications of MAX1997ETJ

• Dc: 0618
• Lead Free Status / Rohs Status: No

A logic-low signal on the SHDN pin disables all device
functions including the reference. During shutdown, the
supply current drops to 0.1µA (typ) to maximize battery
life. The output capacitance, feedback resistors, and load
current determine the rate at which each output voltage
decays. A logic-high signal on the SHDN pin activates the
MAX1997/MAX1998. (See the Power-Up Sequencing
section.) Do not leave the SHDN pin floating. Toggling
SHDN (below 0.4V) or cycling IN (below 2.2V) clears the
fault latch.
Once SHDN is pulled high and the input voltage on IN
exceeds the rising input UVLO threshold (2.7V typ), the
reference turns on. With a 0.22µF REF bypass capacitor,
the reference reaches its regulation voltage of 1.25V in
approximately 1ms. When the reference voltage is ready,
the MAX1997/MAX1998 enable the oscillator and fault
detector. After the oscillator is enabled, the controller
turns on the external P-channel MOSFET P1 (Figure 1) by
pulling GATE low. The GATE is pulled down with a 10µA
current source. Add a capacitor from the gate of P1 to its
drain to slow down the turn-on rate of the MOSFET,
which reduces inrush current.
To guarantee slow turn-on at lower V
resistor between the GATE pin and the gate of the exter-
nal P-channel MOSFET. The typical value of the resistor
ranges between 100kΩ and 200kΩ. Once GATE reaches
approximately 0.6V, an internal N-channel MOSFET turns
on and pulls GATE to ground in order to maximize the
enhancement of the external P-channel MOSFET. After P1
fully turns on, REG 1 and the fault counter are enabled.
A logic-high signal on ONDC enables the main step-up
regulator and the sequence control block. The
sequence control state diagram is shown in Figure 7.
The unique sequence control block allows the positive
gate-driver voltage (V
age (V
(V
at the CT pin is kept discharged until the main step-up
regulator is enabled. An internal 5µA current source
starts charging the CT capacitor and the CT voltage
ramps linearly up to approximately V
and REG 2 are enabled when the CT voltage exceeds
their associated ON_ control inputs. In addition, the
positive linear regulator waits for the completion of the
main step-up regulator soft-start. The positive linear
regulator is controlled by ONP. The negative linear reg-
ulator is controlled by ONN. REG2 and the open-drain
output DRVA are controlled by ON2. The DRVA signal
can be used to turn on an external N-channel MOSFET
Quintuple/Triple-Output TFT LCD Power Supplies
SOURCE
G_OFF
) to be turned on in any order. The capacitor
), and the source-driver supply voltage
______________________________________________________________________________________
Power-Up Sequencing and
G_ON
with Fault Protection and VCOM Buffer
Inrush Current Control
), negative gate-driver volt-
Shutdown (
IN
. REG P, REG N,
IN
, add a series
SHDN )
(N1, Figure 1), which connects the main step-up regu-
lator output to the source driver’s supply pins.
Each positive regulator (MAIN, REG P, REG 1, and REG
2) includes a 5-bit soft-start DAC whose input is the ref-
erence, and whose output is stepped in 32 steps from
zero up to the reference voltage. The soft-start DAC of the
negative regulator (REG N) steps from the reference
down to 125mV in 32 steps. The soft-start duration scales
with the switching frequency selected and is 2.73ms for
1.5MHz operation, 5.46ms for 750kHz operation, and
10.92ms for 375kHz operation.
Figure 7. Power-Up Sequence State Diagram
GATE NOT READY
ENABLE REG P
DONE AND V
ONDC = 0
BOOST SOFT-START
V
CT
GATE NOT READY
< ONP
CT
SHDN = 0 OR
> ONP
V
V
ONDC = 0
PRESENT
CT
IN
V
IN
< 2.7V
> ONN
BIAS, AND UVLO
OC COMP, GATE
NOT
BOOST, VCOM,
ENABLE REG N
ENABLE REG 1
CLEAR FAULT
ENABLE OSC,
ENABLE REF,
SHUTDOWN
AND FAULT
SEQUENCE
COUNTER
ENABLE
BLOCK
V
V
GATE READY
ONDC = 1
SHDN = 1 AND
V
CT
IN
IN
> 2.7V
< ONN
PRESENT
V
CT
V
> ON2
CT
ONDC = 0
< ON2
ENABLE REG 2,
IMPEDANCE
DRVA HIGH
Soft-Start
V
IN
< 2.7V
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