CY7C4292-15ASC Cypress Semiconductor Corp, CY7C4292-15ASC Datasheet - Page 3

• Manufacturer Part Number: CY7C4292-15ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4292-15ASC

• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 128Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06009 Rev. *B
Pin Definitions
Functional Description
The CY7C4282/92 provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to
Empty+7 and Full-7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.5
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Architecture
The CY7C4282/92 consists of an array of 64K to 128K words
of 9 bits each (implemented by a dual-port array of SRAM
cells), a read pointer, a write pointer, control signals (RCLK,
WCLK, REN, WEN, RS), and flags (EF, PAE, PAF, FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q
t
to its default state, the user must not read or write while RS is
LOW. All flags are guaranteed to be valid t
LOW.
RCLK
EF
FF
PAE
PAF/XO
FL/RT
XI/LD
OE
RS
RSF
Signal
Name
after the rising edge of RS. In order for the FIFO to reset
Read Clock
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full/
Expansion Output
First Load/
Retransmit
Expansion
Input/Load
Output Enable
Reset
Description
I/O
(continued)
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
O Dual-Mode Pin. Cascaded – Connected to XI of next device. Not Cascaded – When PAF is
I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty.
I Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to V
I Dual-Mode Pin. Cascaded – Connected to XO of previous device. Not Cascaded – LD is
I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
I Resets device to empty condition. A reset is required before an initial read or write operation
When LD is LOW, RCLK reads data out of the programmable flag-offset register.
programmed into the FIFO. PAE is synchronized to RCLK.
LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO.
PAF is synchronized to WCLK.
other devices will have FL tied to V
to V
by strobing RT.
used to write or read the programmable flag offset registers. LD must be asserted low during
reset to enable standalone or width expansion operation. If programmable offset register
access is not required, LD can be tied to RS directly.
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
after power-up.
SS
RSF
on all devices. Not Cascaded – Retransmit function is available in stand-alone mode
after RS is taken
0 8
) go LOW
During reset of the FIFO, the state of the XI/LD pin determines
if depth expansion operation is used. For depth expansion
operation, XI/LD is tied to XO of the next device. See “Depth
Expansion Configuration” and Figure 3. For standalone or
width-expansion configuration, the XI/LD pin must be asserted
low during reset.
There is a 0-ns hold time requirement for the XI/LD configu-
ration at the RS deassertion edge. This allows the user to tie
XI/LD to RS directly for applications that do not require access
to the flag offset registers.
FIFO Operation
When the WEN is asserted LOW and FF is HIGH, data present
on the D
of the WCLK signal. Similarly, when the REN is asserted LOW
and EF is HIGH, data in the FIFO memory will be presented
on the Q
edge of RCLK while REN is active. REN must set up t
before RCLK for it to be a valid read function. WEN must occur
t
An output enable (OE) pin is provided to three-state the Q
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q
after t
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
even after additional reads occur.
ENS
before WCLK for it to be a valid write function.
CC
OE
0–8
. In standard mode or width expansion, FL is tied
. If devices are cascaded, the OE function will only
Description
0–8
outputs. New data will be presented on each rising
pins is written into the FIFO on each rising edge
CY7C4282
CY7C4292
Page 3 of 16
0–8
0–8
outputs
outputs
SS
; all
ENS
0–8
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