CY7C4292-15ASC Cypress Semiconductor Corp, CY7C4292-15ASC Datasheet - Page 10
![](/photos/31/34/313434/42864tqfp_sml.jpg)
CY7C4292-15ASC
Manufacturer Part Number
CY7C4292-15ASC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C4292-15ASC.pdf
(16 pages)
Specifications of CY7C4292-15ASC
Configuration
Dual
Density
1.125Mb
Access Time (max)
10ns
Word Size
9b
Organization
128Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
40mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4292-15ASC
Manufacturer:
CYPRESS
Quantity:
13 888
Document #: 38-06009 Rev. *B
Switching Waveforms
Notes:
14. t
15. t
Read Cycle Timing
Write Cycle Timing
edge of RCLK and the rising edge of WCLK is less than t
rising edge of WCLK and the rising edge of RCLK is less than t
Q
D
SKEW1
SKEW1
0
0
WCLK
WCLK
RCLK
RCLK
WEN
–D
–Q
WEN
REN
REN
OE
FF
EF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
is also the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
17
17
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
[14]
t
CLKH
CLKH
t
t
t
WFF
A
REF
t
OE
SKEW1
SKEW2
t
t
, then FF may not change state until the next WCLK rising edge.
CLK
CLK
t
SKEW1
NO OPERATION
, then EF may not change state until the next RCLK rising edge.
[15]
t
DS
t
CLKL
t
CLKL
t
ENS
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
t
OHZ
NO OPERATION
CY7C4282
CY7C4292
Page 10 of 16
[+] Feedback