MT46V8M16TG-75EIT Micron Technology Inc, MT46V8M16TG-75EIT Datasheet - Page 58

• Manufacturer Part Number: MT46V8M16TG-75EIT
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V8M16TG-75EIT

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 140mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Figure 31:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
READ-to-PRECHARGE
Notes:
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
DQS
DQS
DQS
1. Provided
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
7. An ACTIVE command to the same bank is only allowed if
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
assumed that
Bank a,
Bank a,
Bank a,
READ
READ
READ
Col n
Col n
Col n
T0
T0
T0
t
RAS (MIN) is met, a READ command with auto precharge enabled would cause a
t
RAS (MIN) is met.
CL = 2
t
AC,
NOP
NOP
NOP
T1
T1
T1
CL = 2.5
t
DQSCK, and
CL = 3
58
(a or all)
(a or all)
(a or all)
Bank a,
Bank a,
Bank a,
PRE
T2
PRE
PRE
T2
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ.
DO
n
T2n
T2n
128Mb: x4, x8, x16 DDR SDRAM
DO
n
T3
NOP
NOP
NOP
T3
T3
DON’T CARE
DO
n
t RP
t RP
t RP
T3n
T3n
T3n
t
RC (MIN) is met.
©2004 Micron Technology, Inc. All rights reserved.
T4
T4
T4
NOP
NOP
NOP
TRANSITIONING DATA
T4n
Operations
Bank a,
Bank a,
Bank a,
T5
T5
T5
Row
Row
Row
ACT
ACT
ACT