PIC16C72A-04/SO Microchip Technology Inc., PIC16C72A-04/SO Datasheet - Page 43

• Manufacturer Part Number: PIC16C72A-04/SO
• Description: 28 PIN, 3.5 KB OTP, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C72A-04/SO

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 4 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

8.3.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT reg-
ister is cleared. The received address is loaded into the
SSPBUF register.
FIGURE 8-3:
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
1999 Microchip Technology Inc.
SSPOV (SSPCON<6>)
S
RECEPTION
A7 A6 A5 A4 A3 A2 A1
1
2
Receiving Address
I
2
3
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
4
5
6
7
R/W=0
8
ACK
9
D7
1
D6
2
SSPBUF register is read
Preliminary
Receiving Data
D5
3
Cleared in software
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
D1
7
D0
8
ACK
9
D7
1
PIC16C62B/72A
D6
2
D5
Receiving Data
3
D4
4
ACK is not sent.
D3
5
D2
6
D1
7
DS35008B-page 43
D0
8
ACK
9
transfer
Bus Master
terminates
P