PIC24FJ32GA002-I/SO Microchip Technology Inc., PIC24FJ32GA002-I/SO Datasheet - Page 211
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PIC24FJ32GA002-I/SO
Manufacturer Part Number
PIC24FJ32GA002-I/SO
Description
MCU, 16-Bit, 28-Pin, 32KB Flash, 8KB RAM, 21 I/O, Nanowatt
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC24FJ32GA002-ISP.pdf
(256 pages)
Specifications of PIC24FJ32GA002-I/SO
A/d Inputs
10 Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/UART
Memory Capacity
32 Kbytes
Memory Type
Flash
Number Of Bits
16
Number Of Inputs
21
Number Of Pins
28
Package Type
28-pin SOIC
Programmable Memory
32K Bytes
Ram Size
8K Bytes
Speed
32 MHz
Timers
5-16-bit
Voltage, Range
2-3.6 V
Voltage, Rating
2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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FIGURE 23-2:
23.3.1
The WDT is enabled or disabled by the FWDTEN
device
Configuration bit is set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
23.4
PIC24FJ64GA004 family devices implement a JTAG
interface, which supports boundary scan device testing
as well as in-circuit programming.
23.5
For all devices in the PIC24FJ64GA004 family of
devices, the on-chip program memory space is treated
as a single block. Code protection for this block is
controlled by one Configuration bit, GCP. This bit
inhibits external reads and writes to the program
memory space. It has no direct effect in normal
execution mode.
© 2007 Microchip Technology Inc.
Sleep or Idle Mode
New Clock Source
All Device Resets
CLRWDT Instr.
PWRSAV Instr.
Exit Sleep or
Transition to
LPRC Input
Configuration
JTAG Interface
Program Verification and
Code Protection
SWDTEN
Idle Mode
FWDTEN
CONTROL REGISTER
WDT BLOCK DIAGRAM
bit.
31 kHz
When
(5-bit/7-bit)
Prescaler
FWPSA
the
1 ms/4 ms
FWDTEN
LPRC Control
PIC24FJ64GA004 FAMILY
Preliminary
Counter
WDT
Write protection is controlled by the GWRP bit in the
Configuration Word. When GWRP is programmed to
‘0’, internal write and erase operations to program
memory are blocked.
23.5.1
The Configuration registers are protected against
inadvertent or unwanted changes or reads in two ways.
The primary protection method is the same as that of
the RP registers – shadow registers contain a compli-
mentary value which is constantly compared with the
actual value.
To safeguard against unpredictable events, Configura-
tion bit changes resulting from individual cell level
disruptions (such as ESD events) will cause a parity
error and trigger a device Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the GCP bit is set, the source data for device
configuration is also protected as a consequence.
WDTPS3:WDTPS0
1:1 to 1:32.768
Postscaler
CONFIGURATION REGISTER
PROTECTION
DS39881B-page 209
WDT Overflow
Wake from Sleep
Reset
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