K4S641632N-LC75000 Samsung Semiconductor, K4S641632N-LC75000 Datasheet - Page 11

• Manufacturer Part Number: K4S641632N-LC75000
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S641632N-LC75000

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/4.5ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 110mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

12.0 AC Operating Test Conditions
13.0 Operating AC Parameter
Notes :
K4S640832N
K4S641632N
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
AC input levels (V
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
6. tRC =tRFC, tRDL = tWR.
(Fig. 1) DC output load circuit
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
and then rounding off to the next higher integer.
870Ω
Parameter
IH
Parameter
/V
IL
)
3.3V
CAS latency = 3
CAS latency = 2
1200Ω
30pF
V
V
tRAS(max)
tRRD(min)
tRCD(min)
tCCD(min)
tRAS(min)
tRDL(min)
tCDL(min)
OH
OL
tDAL(min)
tBDL(min)
Symbol
tRP(min)
tRC(min)
(DC) = 0.4V, I
(DC) = 2.4V, I
11 of 15
OL
OH
50
10
15
15
40
55
= 2MA
= -2MA
2 CLK + tRP
Version
See Fig. 2
tr/tf = 1/1
2.4/0.4
100
Value
60
12
18
18
42
60
2
1
1
1
2
1
1.4
1.4
Output
(AC operating conditions unless otherwise noted)
(Fig. 2) AC output load circuit
75
15
20
20
45
65
Synchronous DRAM
Rev. 1.12 August 2008
(V
Z0 = 50Ω
DD
= 3.3V ± 0.3V, T
Unit
CLK
CLK
CLK
CLK
ea
ns
ns
ns
ns
us
ns
-
V
Unit
50Ω
A
TT
ns
30pF
V
V
V
= 0 to 70°C)
Note
2,5,6
= 1.4V
1, 6
1
1
1
1
5
2
2
3
4