MAX97236EVKIT+ Maxim Integrated Products, MAX97236EVKIT+ Datasheet - Page 31

• Manufacturer Part Number: MAX97236EVKIT+
• Description: Audio Modules & Development Tools MAX97236 Eval Kit
• Manufacturer: Maxim Integrated Products

Specifications of MAX97236EVKIT+

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The IC features an I
serial interface consisting of a serial-data line (SDA) and
a serial-clock line (SCL). SDA and SCL facilitate commu-
nication between the IC and the master at clock rates up
to 400kHz.
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
IC by transmitting the proper slave address followed by
the register address and then the data word. Each trans-
mit sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the IC is 8 bits long and is followed
by an acknowledge clock pulse. A master reading data
from the IC transmits the proper slave address followed
by a series of nine SCL pulses. The IC transmits data on
SDA in sync with the master-generated SCL pulses. The
master acknowledges receipt of each byte of data. Each
read sequence is framed by a START or REPEATED
START condition, a not acknowledge, and a STOP condi-
tion. SDA operates as both an input and an open-drain
output. A pullup resistor, typically greater than 500I,
is required on SDA. SCL operates only as an input. A
pullup resistor, typically greater than 500I, is required
on SCL if there are multiple masters on the bus, or if
the single master has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
resistors protect the digital inputs of the IC from high
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
One data bit is transferred during each SCL cycle. The data
on SDA must remain stable during the high period of the
Figure 10. I
SMBus is a trademark of Intel Corp.
SDA
SCL
t
HD,STA
2
C Interface Timing Diagram
Figure 10
CONDITION
START
shows the 2-wire interface timing
2
t
C/SMBusK-compatible, 2-wire
LOW
I
2
C Serial Interface
Audio Amplifier with Jack Detection
t
R
t
t
SU,DAT
HIGH
t
F
t
HD,DAT
Bit Transfer
t
SU,STA
START CONDITION
SCL pulse. Changes in SDA while SCL is high are control
signals. See the
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high
condition from the master signals the beginning of a
transmission to the IC. The master terminates transmis-
sion and frees the bus by issuing a STOP condition. The
bus remains active if a REPEATED START condition is
generated instead of a STOP condition.
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the
same SCL high pulse as the START condition.
Figure 11. START, STOP, and REPEATED START Conditions
REPEATED
SDA
SCL
t
HD,STA
S
START and STOP Conditions
t
SP
START and STOP Conditions
t
SU,STO
Sr
Early STOP Conditions
CONDITION
(Figure
STOP
t
BUF
11). A START
section.
CONDITION
START
P
31