PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 94

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

U/IOM
LBBD
LB2
LB1
6.2.3
The Block Error Counter register ’RDS’ monitors and counts code violations of the near-
end and far-end side. The counter stops at 255 and does not overflow. If the register is
read out the block error counter is automatically reset to ’0’.
The register value can be requested either by the MON-8 command ’RDS’ or can be
directly addressed using the MON-12 protocol.
RDS
Reset value: 00
Data Sheet
®
7
Close LBBD, LB2, LB1 Towards U or Towards IOM
Switch that selects whether loopback LB1, LB2 or LBBD is closed towards
U or towards IOM
the setting affects all test loops, LBBD, LB2 and LB1
an individual selection for LBBD, LB2, LB1 is not possible
0 =
1 =
Close complete loop (B1, B2, D) near the system interface
the direction towards the loop is closed is determined by bit ’U/IOM
0 =
1 =
Close loop B2 near the system interface
the direction towards the loop is closed is determined by bit ’U/IOM
0 =
1 =
Close loop B1 near the system interface
the direction towards the loop is closed is determined by bit ’U/IOM
0 =
1 =
RDS - Block Error Counter Register
H
6
LB1, LB2, LBBD loops are closed from IOM
LB1, LB2, LBBD loops are closed from U to U
complete loopback open
complete loopback closed
loopback B2 open
loopback B2 closed
loopback B1 open
loopback B1 closed
®
-2
5
Block Error Counter Value
4
read
95
3
2
®
®
-2 to IOM
Register Description
1
Address: 12
®
PEF 24901
-2
2002-09-30
®
®
®
DFE-T
’
’
’
0
H