PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 40

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.3
The interface to the PEF 24902 AFE V2.2 is a 6-wire interface (see
and SDR transmit and receive data is exchanged as well as control information for the
start-up procedure by means of time division multiplexing.
On SDX transmit data, power-up/down information, range function and analog loopback
requests are transferred.
On SDR level status information is received for all line ports.
On PDM0..PDM3 the ADC output data from the AFE is transferred to the DFE-T V2.2.
The timing of all signals is based on the 15.36 MHz master clock which is provided by
the AFE.
Figure 12
The 128 available bits (related to the 15.36 MHz clock) on SDR/SDX during a 120 kHz
period are divided into 9 time-slots. 8 time-slots are 13-bits long and are reserved for
data transmission, 1 time-slot is 24-bits long and used for synchronization purposes. The
DFE-T V2.2 uses four of them, time-slots no. 1, 3, 5 and 7.
assignment of the IOM
of the time-slots to the line ports.
Table 5
IOM
0/4/8/12
1/5/9/13
2/6/10/14
3/7/11/15
Data Sheet
®
-2 Channel No.
Interface to the Analog Front End
AFE V2.1
PEF 24902
Interface to the Analog Front End
Assignments of IOM
Line Ports No.
®
-2 channels to the time-slots on SDX/SDR and the assignment
Time-Slot No.
1
3
5
7
®
Channels to Time-Slots No. on SDX/SDR and
PDM0
PDM1
PDM2
PDM3
SDR
SDX
41
DFE-T V2.2
0
1
2
3
PEF 24901
Line Port No.
Functional Description
Figure
Table 5
dfe_afe_if
12). On SDX
PEF 24901
shows the
2002-09-30
DFE-T