PSB21150HV14XP Infineon Technologies, PSB21150HV14XP Datasheet - Page 143
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PSB21150HV14XP
Manufacturer Part Number
PSB21150HV14XP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21150HV14XP.pdf
(270 pages)
Specifications of PSB21150HV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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3.9
The IPAC-X contains three HDLC controllers which can arbitrarily be used for the layer-2
functions of the D- channel protocol (LAPD) and B-channel protocols. By setting the
Enable HDLC channel bits (EN_D, EN_B1H, EN_B2H) in the DCI_CR/BCH_CR
registers each of the HDLC controllers can access the D or B-channels or any
combination of them e.g. 18-bit IDSL data (2B+D).
They perform the framing functions used in HDLC based communication: flag
generation/recognition, bit stuffing, CRC check and address recognition.
The D-channel FIFO has a size of 64 byte per direction. Each of the two B-channel
FIFOs has a size of 128 bytes per direction. They are implemented as cyclic buffers. The
transceiver reads and writes data sequentially with constant data rate whereas the data
transfer between FIFO and microcontroller uses a block oriented protocol with variable
block sizes.
The configuration, control and status bits related to the HDLC controllers are all assigned
to the following address ranges:
Table 17
D-channel
B-channel A
B-channel B
Note: For B-channel data access a single address location is used to read from and write
The mechanisms for access to the FIFOs are identical for D- and B-channels, therefore
the following description applies to both of them and for simplification specific references
like registers are indicated by an “x” (stands for “D” and “B”) to indicate it is relevant for
D- and B-channel (e.g. ISTAx means ISTAD/ISTAB).
Data Sheet
to the FIFO. For D-channel access the address range 00
in ISAC-S PEB 2086), however a single address from this range is sufficient to
access the FIFO as the internal FIFO pointer is incremented automatically
independent from the external address.
HDLC Controllers
HDLC Controller Address Range
FIFO
Address
00
7A
8A
H
H
H
-1F
H
143
Description of Functional Blocks
Config/Ctrl/Status
Registers
20
70
80
H
H
H
H
-29
-79
-89
-1F
H
H
H
H
PSB/PSF 21150
is used (similar as
2003-01-30
IPAC-X
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