TP3420AV/NOPB National Semiconductor, TP3420AV/NOPB Datasheet
TP3420AV/NOPB
Specifications of TP3420AV/NOPB
Related parts for TP3420AV/NOPB
TP3420AV/NOPB Summary of contents
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... Adaptive receive signal processing ensures low bit error rates on any of the standard types of cable pairs commonly found in premise wiring installations when tested with the noise sources specified in I.430. TRI-STATE ® registered trademark of National Semiconductor Corporation. COMBO ™ , MICROWIRE ™ and SID ™ ...
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Block Diagram Connection Diagrams TP3420A SID Order Number TP3420AV See NS Package Number V20A TP3420A SID Top View Order Number TP3420AJ or TP3420AN See NS Package Number J20A or N20A www.national.com Pin Descriptions Name GND Negative power supply pin, normally ...
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Pin Descriptions (Continued) Name Description modes and TES mode, this pin is a the Transmit Frame Sync pulse TTL/CMOS input, requiring a positive edge to indicate the start of the active channel time for transmit “B” and ...
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Pin Descriptions (Continued) TABLE 1. Alternate Pin Function Assignment Device P2 - Pin 8 Mode Function x Function 2 TEM DENx 0 LSD (Note 3) (Note 3) SCLK 1 DENr SCLK DENx TES DENx 0 LSD SCLK 1 DENr (Note ...
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Functional Description (Continued) + − boundary, by using a 0 bit followed dicate the start of a frame, and forcing the first binary zero following the balance bit the same polarity as the bal- ...
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Functional Description www.national.com (Continued) 6 ...
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Functional Description (Continued) DIGITAL SYSTEM INTERFACE The Digital System Interface (DSI) on the TP3420A com- bines “B” and “D” channel data onto common pins to provide maximum flexibility with minimum pin count. Several multi- plexed formats of the B and ...
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Functional Description Note: In TES mode, DENx outputs SCLK synchronized to the S interface. Format 1, SCLK = 2.048 MHz, Format 2, SCLK = 256 kHz, Format 3, * SCLK = 512 kHz, Format 4, SCLK = 2.56 MHz. FIGURE ...
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Functional Description (Continued) * Note: DENR signal is available on pin 18 after using the PINDEF command (see Table 1 ). FIGURE 4. Digital System Interface Formats in TEM mode (DSI Master) Format 1 DS009143-14 Format 2 Format 3 Format ...
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Functional Description FIGURE 5. TP3240A Enhanced MICROWIRE Control Interface Timing Function Activation/Deactivation No Operation Power-Down (Note 6) Power-Up Deactivation Request Force INFO2 (NT only) Monitor Mode Activation Activation Request Device Modes NT Mode, Adaptive Sampling (Note 6) NT Mode, Fixed ...
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Functional Description (Continued) TABLE 4. Control Register Functions (Continued) Function D Channel Access D Channel Request, Class 1 Message D Channel Request, Class 2 Message D Channel Access Control Enable D-Channel Access Mechanism, TE Mode (Note 8) Disable D-Channel Access ...
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Functional Description (Continued) TABLE 4. Control Register Functions (Continued) Function Control Device State Reading Disable the Device State Output on the NOCST (Note 6) Control of Additional Interrupts Enable the Slip and RMFE Interrupts Disable the Slip and RMFE Interrupts ...
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Functional Description (Continued) a packet in the D channel, a received E bit does not match the last transmitted D bit, indicating a lost collision. AI This interrupt indicates that the interface has been successfully Activated in response to an ...
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Functional Description DIGITAL INTERFACE FORMATS DIF1) These instructions select the format of the Digital Interface timing, see Figure 3 and DIF2) DIF3) Figure 4 . DIF4) BCLK FREQUENCY SETTINGS BCLK1 These instructions change the frequency of a BCLK2 selected Digital ...
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Functional Description (Continued) MULTIFRAME TRANSMIT AND RECEIVE REGISTERS MFT1L) With the device in TE Mode, data entered in MFT1H) M1, M2, M3 and M4 bits of MTF1L is MFT2) transmitted towards the NT in multiframe bit MFR1) positions Q1, Q2, ...
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Functional Description 3. Contiguous B1+B2 (128 kbit/s) digital loopback (LBB1, LBB2) in TEM mode and in NT/TES modes if FSa is phase synchronous with FSb. 4. Contiguous B1+B2+D (144 kbit/s) digital loopback (LBD) in TEM mode and in NT/TES modes ...
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Functional Description (Continued being received, the loop is de-activated, Status Indica- tion type DI is set and the INT output pulled low to indicate De-activation. I.430 does not provide for Deactivation to be initiated by a TE. However, ...
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Functional Description EBIT0 command forces the E bit to 0 continuously to simu- late the effect of a busy D channel. The D channel access al- gorithm can be verified by releasing the E-bit control using the EBITNRM command. Alternatively, ...
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Functional Description (Continued multiframe counter (30 ms) in the TP3420A is enabled by the MFC6E command, and disabled with the MFC6D command. When the counter is enabled (MFC6E), an inter- rupt MFC is generated locally every 30 ms ...
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Functional Description TABLE 8. Codes for SC1, SC2 and Q Channel Messages with 3X Checking Enabled SCI Messages Received at TE S11 S12 S13 S14 Idle (NORMAL Loss-of-Power 1 1 Indication STP Self Test Pass 0 0 ...
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Functional Description (Continued) BIPOLAR VIOLATION DETECTION AND FECV MESSAGING VIA THE SC1 CHANNEL NT Mode A Receive Multiframe Error (RMFE) detector circuit in the TP3420A identifies any multiframes in which one or more bi- polar violations is received, indicating a ...
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Typical Applications www.national.com 22 ...
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Typical Applications (Continued) POPULAR MICROWIRE FORMATS The TP3420A enhanced MICROWIRE port supports two popular formats used in typical terminal equipment applica- tions. 1. CCLK idling LOW when the CS pin is inactive HIGH, pulsing LOW/HIGH/LOW for 8 clocks then returning ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications GND CC Voltage Voltage at any Digital Input V Electrical Characteristics Unless otherwise noted: limits printed in bold characters are electrical testing limits at V ± ...
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Timing Characteristics Symbol Parameter MCLK SYSTEM CLOCK (See Figure Master Clock Frequency MCK Master Clock Tolerance MCLK/XTAL Input Clock Jitter t , Clock Pulse Width & Low for MCLK Rise and ...
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Timing Characteristics (Continued) Symbol Parameter DIGITAL SYSTEM INTERFACE (See Figure Hold Time, BCLK High HCFH to FS and FS High (Inputs Set up Time, FS and SFC a FSb Inputs to BCLK Low t ...
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Timing Diagrams (Continued) FIGURE 10. Timing Details for Digital System Interface FIGURE 11. Timing Details for TEM, DCKE Mode Definitions and Timing Conventions DEFINITIONS the d.c. input level above which input level is guaranteed ...
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Definitions and Timing Conventions (Continued the maximum d.c. output level which an output placed in a logical zero state will converge when loaded at the maximum specified load current. Threshold Region The threshold region ...
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MFT1H FIFO, if not, then the data from the MFT1L register is sent. If both the buffers are full, then a third ...
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SC1 Messaging Sequence Time SC1 (ms) I430 Frame Content 0 (MFC INT) (LRS) 5 (LRS) 10 (LRS) 15 (LRS) 20 (LRS) 25 (LRS) 0 (MFC INT) (IDLE) 5 (IDLE) 10 (IDLE) 15 (IDLE) 20 (IDLE) 25 (IDLE) 0 (MFC INT) ...
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Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) Order Number TP3420AJ NS Package Number J20A Molded Dual-In-Line Package (N) Order Number TP3420AN NS Package Number N20A 31 www.national.com ...
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