TP3420A National Semiconductor, TP3420A Datasheet
TP3420A
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TP3420A Summary of contents
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... TP3420A ISDN S/T Interface Device General Description The TP3420A is an enhanced version of the TP3420, with a number of upgraded features for compliance with the new release of ANSI T1.605-1991 and CCITT I-430. At initial power-up the device is fully backwards compatible with the TP3420 device, and modifications to the firmware are only required to take advantage of the new features ...
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... Block Diagram Connection Diagrams TP3420A SID Order Number TP3420AV See NS Package Number V20A TP3420A SID Top View Order Number TP3420AJ or TP3420AN See NS Package Number J20A or N20A www.national.com Pin Descriptions Name GND Negative power supply pin, normally 0V (ground). All analog and digital signals are referenced to this pin ...
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... Transmit data at the B input intended to be gated with BCLK to control the shifting of data from layer 2 device to the TP3420A transmit buffer modes, this pin by default is a pulse output (DEN ) which occurs in ...
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... D channel Transmit data at the B input intended to be gated with BCLK to control x the shifting of data from a layer 2 device to the TP3420A’s transmit buffer mode, this pulse occurs every 8 kHz frame and indicates the location of D channel data input on the B pin ...
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... TE mode Digital System Interface Master, or may be slaved to an external source the T-interface side of an NT-2 (TES mode). In TES and NT modes, re-timing circuitry on the TP3420A allows the MCLK frequency to be plesio- chronous (i.e., free-running) with respect to the network clock, i.e. the 8 kHz FS oscillator of 15.36 MHz DPLL allows the network clock frequency to deviate up to ± ...
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Functional Description www.national.com (Continued) 6 ...
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... FS input and the received I.430 frame. JITTER ABSORPTION AND PHASE WANDER BUFFERS The TP3420A has an improved serial data buffer circuit to handle larger amounts of phase wander exceeding the specification of 18 µs pk-to-pk, regardless of the phase dif- ference between the transmit and receive frames. A SLIP in- ...
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Functional Description Note: In TES mode, DENx outputs SCLK synchronized to the S interface. Format 1, SCLK = 2.048 MHz, Format 2, SCLK = 256 kHz, Format 3, * SCLK = 512 kHz, Format 4, SCLK = 2.56 MHz. FIGURE ...
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Functional Description (Continued) * Note: DENR signal is available on pin 18 after using the PINDEF command (see Table 1 ). FIGURE 4. Digital System Interface Formats in TEM mode (DSI Master) Format 1 DS009143-14 Format 2 Format 3 Format ...
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Functional Description FIGURE 5. TP3240A Enhanced MICROWIRE Control Interface Timing Function Activation/Deactivation No Operation Power-Down (Note 6) Power-Up Deactivation Request Force INFO2 (NT only) Monitor Mode Activation Activation Request Device Modes NT Mode, Adaptive Sampling (Note 6) NT Mode, Fixed ...
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Functional Description (Continued) TABLE 4. Control Register Functions (Continued) Function D Channel Access D Channel Request, Class 1 Message D Channel Request, Class 2 Message D Channel Access Control Enable D-Channel Access Mechanism, TE Mode (Note 8) Disable D-Channel Access ...
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Functional Description (Continued) TABLE 4. Control Register Functions (Continued) Function Control Device State Reading Disable the Device State Output on the NOCST (Note 6) Control of Additional Interrupts Enable the Slip and RMFE Interrupts Disable the Slip and RMFE Interrupts ...
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... Again, the DSI is a slave to external BCLK and FS sources. TEM TE Mode DSI Master should be selected when the de- vice TE. The TP3420A is then the source of the BCLK and FS signals, and access to the Transmit D channel, including the priority and contention resolu- tion control, is enabled as described in the section on TE Mode D-Channel Access ...
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... BEX and B1E commands. D CHANNEL ACCESS DREQ1) This is a request from Layer 2 device to the DREQ2) TP3420A (in the TE modes) to attempt to transmit a D channel message at the S interface. Use DREQ1 to select the access priority for a Class 1 message (Q.931 Signaling), or DREQ2 for a Class 2 message ...
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... TP3420 device, and hence software written for a TP3420 is applicable for a TP3420A device. Additional de- vice features may be invoked by MICROWIRE commands. A simple way of identifying a TP3420A from a TP3420 is as fol- lows: Upon application of power, write ENST followed by DISST MICROWIRE commands to the device and evaluate the NOCST status word ...
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... Status Indication type AI is set, and the INT output pulled low. Activation initiated from the NT: when Activation is initiated by the NT, if the TP3420A in TE mode is powered down, it will pull the LSD pin and INT low on receiving a line signal. Either of these can be used to “wake-up” a microprocessor. ...
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... D-channel buffer. (Note not necessary to flush the Layer 2 HDLC transmitter prior to clocking out the open- ing flag; the TP3420A will continue the pre-fetch until the flag is uniquely recognized.) Meanwhile, the Priority Counter checks that no other TE connected to the S interface (in a point-to-multipoint wiring configuration) is transmitting in the D-channel. This is assured by counting consecutive “ ...
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... SC1/Q Transmit Registers For both NT and TE modes, the TP3420A has two registers to transmit a SC1/Q channel message through two MI- CROWIRE commands: MFT1L and MFT1H. Normally the message in MFT1L is transmitted continually. However a high priority message may be loaded in the MFT1H register and transmitted once only ...
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... Functional Description (Continued multiframe counter (30 ms) in the TP3420A is enabled by the MFC6E command, and disabled with the MFC6D command. When the counter is enabled (MFC6E), an inter- rupt MFC is generated locally every 30 ms and internal logic ensures that the MFT1L messages are transmitted 6 times unless interrupted by an MFT1H message ...
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Functional Description TABLE 8. Codes for SC1, SC2 and Q Channel Messages with 3X Checking Enabled SCI Messages Received at TE S11 S12 S13 S14 Idle (NORMAL Loss-of-Power 1 1 Indication STP Self Test Pass 0 0 ...
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... Figure 6 shows a typical application of the TP3420A in an ISDN Terminal. For more in-depth information on a variety of applications, Application Note AN665 is a comprehensive guide to the hardware and software required to meet the I.430 interface specification ...
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Typical Applications www.national.com 22 ...
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... LOW for idle condition. Data is output on the CO pin on the negative edge and data is sampled in on the FIGURE 7. TP3420A Normal MICROWIRE Clock Format FIGURE 8. TP3420A Alternate MICROWIRE Clock Format positive edge of CCLK. This format (shown in Figure normally used with NSC’s microcontrollers from the HPC or the COP8 family ...
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... Note 27: Using a 2:1 PE64995 transformer and a connecting cord. See AN-872 (TP3420A Line Interface or Circuit Considerations) for more details. www.national.com (Note 24) Storage Temperature Range ...
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Timing Characteristics Symbol Parameter MCLK SYSTEM CLOCK (See Figure Master Clock Frequency MCK Master Clock Tolerance MCLK/XTAL Input Clock Jitter t , Clock Pulse Width & Low for MCLK Rise and ...
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Timing Characteristics (Continued) Symbol Parameter DIGITAL SYSTEM INTERFACE (See Figure Hold Time, BCLK High HCFH to FS and FS High (Inputs Set up Time, FS and SFC a FSb Inputs to BCLK Low t ...
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Timing Diagrams (Continued) FIGURE 10. Timing Details for Digital System Interface FIGURE 11. Timing Details for TEM, DCKE Mode Definitions and Timing Conventions DEFINITIONS the d.c. input level above which input level is guaranteed ...
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... LP, FECV, and DTSE commands. These messages should be sent through the MFT1H register. As part of the TP3420A initialization, the software should write the MFC6E command to cause the de- vice to generate the MFC interrupt every 30 ms, and this in- terrupt status should be used to synchronize the SC1L and any SC2 messages ...
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MFT1H FIFO, if not, then the data from the MFT1L register is sent. If both the buffers are full, then a third ...
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SC1 Messaging Sequence Time SC1 (ms) I430 Frame Content 0 (MFC INT) (LRS) 5 (LRS) 10 (LRS) 15 (LRS) 20 (LRS) 25 (LRS) 0 (MFC INT) (IDLE) 5 (IDLE) 10 (IDLE) 15 (IDLE) 20 (IDLE) 25 (IDLE) 0 (MFC INT) ...
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... Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) Order Number TP3420AJ NS Package Number J20A Molded Dual-In-Line Package (N) Order Number TP3420AN NS Package Number N20A 31 www.national.com ...
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... Italiano National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Order Number TP3420AV NS Package Number V20A 2. A critical component is any component of a life support ...