MC145574APBR2 Freescale Semiconductor, MC145574APBR2 Datasheet - Page 77

• Manufacturer Part Number: MC145574APBR2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574APBR2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
BR10
BR12
BR13
BR14
BR15
BR11
BR2
BR3
BR4
BR5
BR6
BR7
BR9
9.1
Do Not React
Transparent
Procedures
Loopback
Activation
to INFO 1
Reserved
Reserved
TXSC2.1
TXSC4.1
NT1 Star
INTRODUCTION
There are 16 byte registers (BR0 through BR15) in the MC145574. Control, status, and maintenance
information reside in these byte registers, which are accessed via the SCP. For a detailed description
of access procedures, refer to Section 5. The nomenclature used in this data sheet is such that BR2(3)
refers to byte register 2, bit 3.
The byte register map is fully compatible with the byte register map of the MC145474, with the exception
of:
1. The functions that were related to the IDL2 A/M FIFOs have been removed. Writing to these registers
2. The TTL input level bit BR13(6) has been removed. The digital inputs are CMOS and TTL compatible.
3. The only addition to the byte register map is the bit BR15(0), used for enabling the overlay registers.
Disabled
Register
Enabled
Overlay
B1 S/T
SC1.1
BPV7
Mode
FV7
Q.1
(7)
has no effect, and reading them returns FFH.
Writing to this bit has no effect, and reading it returns 0 or 1 depending on what value, if any, has been
written.
Table 9–1. Byte Register Map for NT Mode of Operation
Do Not React
Transparent
Active Only
NT Enable
Loopback
to INFO 3
Reserved
Reserved
Reserved
TXSC2.2
TXSC4.2
B1 S/T
SC1.2
BPV6
Non–
FV6
Q.2
(6)
Freescale Semiconductor, Inc.
BYTE REGISTER MAP DESCRIPTION
For More Information On This Product,
Speed (MSB)
Transparent
Multiframing
IDL2 Clock
Loopback
Reserved
Reserved
TXSC2.3
TXSC4.3
Rx INFO
State B1
Enable
B2 S/T
SC1.3
Rev 5
BPV5
FV5
Q.3
(5)
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MC145574
Transparent
on IDL2 Tx
Loopback
Reserved
Reserved
TXSC2.4
TXSC4.4
Rx INFO
State B0
Channel
Mute B2
Invert E
B2 S/T
SC1.4
BPV4
Rev 4
Non–
FV4
Q.4
(4)
IDL2 Master
Transparent
on IDL2 Tx
Loopback
Reserved
Reserved
TXSC3.1
TXSC5.1
State B1
Tx INFO
Mute B1
IDL2 B1
Q Qual
BPV3
Rev 3
Mode
FV3
(3)
Speed (LSB)
Transparent
Force Echo
IDL2 Clock
Multiframe
Loopback
Reserved
Reserved
Interrupt
TXSC3.2
TXSC5.2
State B0
Tx INFO
Channel
IDL2 B1
to Zero
Every
BPV2
Rev 2
Non–
FV2
(2)
External S/T
Transparent
Applicable
Loopback
Loopback
Reserved
Reserved
TXSC3.3
TXSC5.3
IDL2 B2
Polarity
Control
LAPD
Rev 1
BPV1
FV1
Not
(1)
Transparent
Test Signal
Loopback
Activation
Reserved
Reserved
Reserved
Timer #2
TXSC3.4
TXSC5.4
Transmit
IDL2 B2
Expired
96 kHz
Rev 0
BPV0
Non–
FV0
(0)
9
9–1