MC145574APBR2 Freescale Semiconductor, MC145574APBR2 Datasheet - Page 40

• Manufacturer Part Number: MC145574APBR2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574APBR2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

5–2
5.2.2
back high after the transaction, before another rising edge of SCPCLK is encountered. Note that
SCP Rx is ignored during the time that SCP Tx is being driven. Also note that SCP Tx comes out
of high impedance only when it is transmitting data.
SCP Nibble Register Write
A nibble register write is an 8–bit SCP transaction. Figure 5–2 illustrates this process. To initiate an
SCP nibble register write, the SCPEN pin must be brought low. Following this, an R/W bit followed
by three primary address bits are shifted (MSB first) into an intermediate buffer register on the first
four rising edges of SCPCLK following the high–to–low transition of SCPEN. If a write operation is
to be performed, then R/W should be a 0. The three address bits, clocked in after the R/W bit, select
the nibble register to be written to. The data shifted in on the next four rising edges of SCPCLK is
then written to the selected register. Throughout this whole operation the SCP Tx pin remains in high–
impedance state. Note that if a selected register or bit in a selected register is “read only”, then a
write operation has no effect.
SCPCLK
SCP Rx
SCPEN
SCP Tx
Figure 5–1. Serial Control Port Nibble Register Read Operation
Figure 5–2. Serial Control Port Nibble Register Write Operation
NOTES:
SCPCLK
R/W
SCP Rx
SCPEN
SCP Tx
Freescale Semiconductor, Inc.
1. R/W = 0 for a read operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Rx on the rising edges of SCPCLK, MSB first.
4. A2, A1, A0 = 0 to 6.
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A2
A1
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A0
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D3
MC145574
D2
R/W
D1
A2
D0
A1
HIGH IMPEDANCE
A0
D3
D2
D1
HIGH IMPEDANCE
D0
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