PSB21383HV13XP Lantiq, PSB21383HV13XP Datasheet - Page 69

• Manufacturer Part Number: PSB21383HV13XP
• Manufacturer: Lantiq

Specifications of PSB21383HV13XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

2.2.4.5
To prevent lock-up situations in a MONITOR transmission a time-out procedure can be
enabled by setting the time-out bit (TOUT) in the MONITOR configuration register
(MCONF). An internal timer is always started when the transmitter must wait for the reply
of the addressed device or for transmit data from the microcontroller. After 40 IOM
frames (5ms) without reply the timer expires and the transmission will be aborted.
2.2.4.6
Figure 36 shows the MONITOR interrupt structure of the SCOUT. The MONITOR Data
Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable
(MRE) and MR bit Control (MRC). The MONITOR channel End of Reception MER,
MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB
interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE.
MRE inactive (0) prevents the occurrence of MDR status, including when the first byte of
a packet is received. When MRE is active (1) but MRC is inactive, the MDR interrupt
status is generated only for the first byte of a receive packet. When both MRE and MRC
are active, MDR is always generated and all received MONITOR bytes - marked by a 1-
to-0 transition in MX bit - are stored. (Additionally, an active MRC enables the control of
the MR handshake bit according to the MONITOR channel protocol.)
Figure 36
MONITOR Interrupt Structure
Data Sheet
TRAN
MASK
HDLC
WOV
MOS
CIC
TIN
INT
ST
MONITOR Time-Out Procedure
MONITOR Interrupt Logic
TRAN
HDLC
ISTA
WOV
MOS
CIC
TIN
ST
59
MOCR
MRE
MIE
MOSR
MER
MDR
MDA
MAB
PSB 21381/2
PSB 21383/4
Interfaces
2001-03-12