PSB21383HV13XP Lantiq, PSB21383HV13XP Datasheet - Page 193

• Manufacturer Part Number: PSB21383HV13XP
• Manufacturer: Lantiq

Specifications of PSB21383HV13XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

7.1.4
Value after reset: FC
MASKH
Each interrupt source in the ISTAH register can be selectively masked by setting to ’1’
the corresponding bit in MASK. Masked interrupt status bits are not indicated when
ISTAH is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
7.1.5
Value after reset: 40
STAR
XDOV
More than 16/32 bytes have been written in one pool of the XFIFO, i.e. data has been
overwritten.
XFW
Data can be written in the XFIFO. This bit may be polled instead of (or in addition to)
using the XPR interrupt.
RACI
The HDLC receiver is active when RACI = ’1’. This bit may be polled. The RACI bit is set
active after a begin flag has been received and is reset after receiving an abort
sequence.
XACI
The HDLC-transmitter is active when XACI = ’1’. This bit may be polled. The XACI-bit is
active when an XTF-command is issued and the frame has not been completely
transmitted.
Data Sheet
MASKH - Mask Register HDLC
STAR - Status Register
XDOV XFW
7
7
RME
... Transmit Data Overflow
... Transmit FIFO Write Enable
... Receiver Active Indication
... Transmitter Active Indication
RPF
H
H
RFO
0
XPR
0
183
RACI
XMR
XDU
0
Detailed Register Description
XACI
0
0
0
0
0
PSB 21381/2
PSB 21383/4
2001-03-12
WR (20
RD (21
H
H
)
)