PSF21150F-V14 Infineon Technologies, PSF21150F-V14 Datasheet - Page 242
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PSF21150F-V14
Manufacturer Part Number
PSF21150F-V14
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSF21150F-V14.pdf
(270 pages)
Specifications of PSF21150F-V14
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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IPAC-X
PSB/PSF 21150
Electrical Characteristics
5.6
IOM-2 Interface Timing
Data is transmitted with the rising edge of DCL and sampled with its falling edge. Below
figure shows double clock mode timing (the length of a timeslot is 2 DCL cycles),
however, the timing parameters are valid both in single and double clock mode. For the
direction of DU,DD (input or output) please refer to
Chapter
3.4.
Figure 91
IOM-2 Timing (TE mode)
Data Sheet
242
2003-01-30
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