PSB3186FV14XP Infineon Technologies, PSB3186FV14XP Datasheet - Page 61
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PSB3186FV14XP
Manufacturer Part Number
PSB3186FV14XP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB3186FV14XP.pdf
(200 pages)
Specifications of PSB3186FV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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Figure 34
3.5.1.2
F3 Pending Deactivation
State after deactivation from the S/T interface by info 0. Note that no activation from the
terminal side is possible starting from this state. A ’DI’ command has to be issued to enter
the state ’Deactivated State’.
F3 Deactivated State
The S/T interface is deactivated and the clocks are deactivated 500 µs after entering this
state and receiving info 0 if the CFS bit of the ISAC-SX TE Configuration Register is set
to “0“. Activation is possible from the S/T interface and from the IOM-2 interface.
F3 Power Up
The S/T interface is deactivated (info 0 on the line) and the clocks are running.
F4 Pending Activation
The ISAC-SX transmits info 1 towards the network, waiting for info 2.
F5 Unsynchronized
Any signal except info 2 or 4 detected on the S/T interface.
F6 Synchronized
The receiver has synchronized and detects info 2. Info 3 is transmitted to synchronize
the NT.
Data Sheet
TIM
DI
States (TE)
Test Mode i
TMA
it
State Transition Diagram of Unconditional Transitions (TE)
i
SSP
SCP
SSP
SCP
*
TIM
DI
TIM
DI
Loop A Activated
Loop A Closed
ARL ARL
RSY
AIL
i3
i3
ARL
i3
ARL
61
*
*
i3
Description of Functional Blocks
TIM
DI
RES RES
i0
Reset
State
Any
RES
*
ISAC-SX TE
RST
PSB 3186
2003-01-30
statem_te_aloop_s.vsd
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