PSF21150HV14NP Infineon Technologies, PSF21150HV14NP Datasheet - Page 138
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PSF21150HV14NP
Manufacturer Part Number
PSF21150HV14NP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSF21150HV14NP.pdf
(270 pages)
Specifications of PSF21150HV14NP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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DCL is activated such that its first rising edge occurs with the beginning of the bit
following the C/I (C/I0) channel.
After the clocks have been enabled this is indicated by the PU code in the C/I channel
and, consequently, by a CIC interrupt. The DU line may be released by resetting the
Software Power Up bit IOM_CR =’0’ and the C/I code written to CIX0 before (e.g. TIM or
AR8) is output on DU.
The IPAC-X supplies IOM-2 timing signals as long as there is no DIU command in the
C/I (C/I0) channel. If timing signals are no longer required and activation is not yet
requested, this is indicated by programming DIU in the CIX0 register.
Figure 78
Data Sheet
FSC
DU
DD
FSC
DU
DD
DCL
SPU = 1
Activation of the IOM-2 interface
0.2 to 4 ms
Note: The value “132 x DCL” is only valid for
IOM configurations with 3 IOM channels.
MR
MX
IOM -CH1
IOM
132 x DCL
R
R
-CH1
138
PU
IOM -CH2
IOM -CH2
R
R
Description of Functional Blocks
CIC : CIXO = TIM
Int.
PU
SPU = 0
B1
B1
TIM
PU
ITD09656
TIM
PU
PSB/PSF 21150
TIM
PU
2003-01-30
IPAC-X
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