PEF24901HV22XP Lantiq, PEF24901HV22XP Datasheet - Page 80

• Manufacturer Part Number: PEF24901HV22XP
• Manufacturer: Lantiq

Specifications of PEF24901HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

4.4.2
The DFE-T V2.2 provides a block error counter per channel. This feature allows
monitoring the transmission quality on the U-interface.
On the NT side a block error is given, if a U-frame with at least one code violation has
been detected (near-end block error). In the following frame the NT transmits a positive
M-symbol upstream.
On the LT side a block error is given, if a U-frame with at least one code violation has
been detected (near-end block error) or a positive M-symbol has been received from the
NT (far-end block error).
The current status of the block error counter can be retrieved by the IOM-2 interface.
When the block error counter is read (via MON-8 command RDS or MON-12 read
access to register RDS), it is automatically reset. The counter is enabled in all states
listed in
value (255).
Table 16
U
Link to TE Synch.
Wait 1ms
Transparent
Note that every frame with a detected code violation causes about 10 to 20 binary bit
errors on average. So a bit error rate of 10
frame errors within 1000 s in the LT (1 frame error detected in the NT and transmitted
via M-symbol).
4.4.3
For bit error rate monitoring the DFE-T V2.2 features an 16-bit Bit Error Rate counter
(BERC) per line. The function is channel selective. The measurement is performed for
the B1, B2 and the D channel. Prerequisite is that loop #2 of the addressed line port has
been closed before on the NT side via the M-channel.
Operation:
• The respective loopback command has to be transmitted to the NT.
• The system sets the respective channel to ’all zeros’.
• The respective lineport is addressed by setting the LP_SEL register.
• The BERC counter is reset to ’0000’ by reading the low significant BERC register.
• The BERC counter can be started after some time (full round trip delay) by selecting
Data Sheet
k0
the channel (s) to be checked in bits TEST.BER.
Synch. no TE ?
Table 16
Block Error Counter (RDS Error Counter)
Bit Error Rate Counter
Active States
and reset in all other states. The counter is saturated at its maximum
–7
81
in both directions is equivalent to 2 detected
Operational Description
PEF 24901
2002-09-30
DFE-T