PSB21150FV14NP Lantiq, PSB21150FV14NP Datasheet - Page 181

• Manufacturer Part Number: PSB21150FV14NP
• Manufacturer: Lantiq

Specifications of PSB21150FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

RBCLD
RBCHD
TEI1
4.1.12
Value after reset: 00
RBC7-0 ... Receive Byte Count
Eight least significant bits of the total number of bytes in a received message (see
RBCHD register).
4.1.13
Value after reset: 00
OV ... Overflow
A ’1’ in this bit position indicates a message longer than (2
RBC8-11 ... Receive Byte Count
Four most significant bits of the total number of bytes in a received message (see
RBCLD register).
Note: Normally RBCHD and RBCLD should be read by the microcontroller after an
4.1.14
Value after reset: FF
Data Sheet
RME-interrupt in order to determine the number of bytes to be read from the
RFIFOD, and the total message length. The contents of the registers are valid only
after an RME or RPF interrupt, and remain so until the frame is acknowledged via
the RMC bit or RRES.
7
7
7
RBC7
RBCLD - Receive Frame Byte Count Low D-Channel
RBCHD - Receive Frame Byte Count High D-Channel
TEI1 - TEI1 Register 1
0
H
H
H
0
.
0
TEI1
OV
181
RBC11
Detailed Register Description
12
- 1) = 4095 bytes .
0
0
0
RBC0
RBC8
EA1
PSB/PSF 21150
2003-01-30
IPAC-X
WR (27)
RD (26)
RD (27)