PSB21150FV14NP Lantiq, PSB21150FV14NP Datasheet - Page 154

• Manufacturer Part Number: PSB21150FV14NP
• Manufacturer: Lantiq

Specifications of PSB21150FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

3.9.3
3.9.3.1
The cyclic transmit FIFO buffers with a length of 64-byte for D-channel and 128 byte for
each of the two B-channels have variable FIFO block sizes (thresholds) of
• 16 or 32 bytes for D-channel and
• 32 or 64 bytes for B-channels
which can be selected by setting the corresponding XFBS bits in the EXMx registers.
There are three different interrupt indications in the ISTAx registers concerned with the
transmission of data:
XPR (Transmit Pool Ready) interrupt, indicating that a data block of up to 16 or 32 byte
(D-channel), 32 or 64 byte (B-channel) can be written to the XFIFOx (block size selected
via EXMx.XFBS).
An XPR interrupt is generated either
– XDU (Transmit Data Underrun) interrupt, indicating that the transmission of the
– Only valid for D-channel:
– XTF (Transmit Transparent Frame) command, telling the IPAC-X that up to 16 or 32
– XME (Transmit Message End) command, telling the IPAC-X that the last data block
– XRES (Transmitter Reset) command, resetting the HDLC transmitter and clearing the
Data Sheet
• after an XRES (Transmitter Reset) command (which is issued for example for frame
abort) or
• when a data block from the XFIFOx is transmitted and the corresponding FIFO
space is released to accept further data from the host.
current frame has been aborted (seven consecutive ’1’s are transmitted) as the
XFIFOx holds no further transmit data. This occurs if the host fails to respond to an
XPR interrupt quickly enough.
XMR (Transmit Message Repeat) interrupt, indicating that the transmission of the
complete last frame has to be repeated as a collision on the S bus has been detected
and the XFIFOx does not hold the first data bytes of the frame (collision after the 16th/
32nd byte or after the 32nd/64th byte of the frame, respectively).
The occurence of an XDU or XMR interrupt clears the XFIFOx and an XMR interrupt
is issued together with an XDU or XMR interrupt, respectively. Data cannot be written
to the XFIFOx as long as an XDU/XMR interrupt is pending.
Three different control commands are used for transmission of data:
byte (D-channel) or 32 or 64 byte (B-channel) have been written to the XFIFOx and
should be transmitted. A start flag is generated automatically.
written to the XFIFOx completes the corresponding frame and should be transmitted.
This implies that according to the selected mode a frame end (CRC + closing flag) is
generated and appended to the frame.
transmit FIFO of any data. After an XRES command the transmitter always sends an
abort sequence, i.e. this command can be used to abort a transmission. Pending
Data Transmission
Structure and Control of the Transmit FIFO
154
Description of Functional Blocks
PSB/PSF 21150
2003-01-30
IPAC-X