PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 9

• Manufacturer Part Number: PDLXT310NE.D4
• Manufacturer: Intel

Specifications of PDLXT310NE.D4

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Not Compliant

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2.1
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2.2
Datasheet
Functional Description
The LXT310 is a fully integrated PCM transceiver for 1.544 Mbps (T1) applications. It allows
full-duplex transmission of digital data over existing twisted-pair installations.
The LXT310 interfaces with two twisted-pair lines (one pair for transmit, one pair for receive)
through standard pulse transformers and appropriate resistors.
The figure on the front page of this section is a block diagram of the LXT310. The transceiver may
be controlled by a microprocessor through the serial port (Host mode), or by individual pin settings
(Hardware mode). The jitter attenuator may be positioned in either the transmit or receive path.
Power Requirements
The LXT310 is a low-power CMOS device. It operates from a single +5 V power supply which
can be connected externally to both the transmitter and receiver. However, the two inputs must be
within ±0.3 V of each other, and decoupled to their respective grounds separately. Refer to
Application Information for typical decoupling circuitry. Isolation between the transmit and
receive circuits is provided internally.
Initialization and Reset Operations
Upon power up, the transceiver is held static until the power supply reaches approximately 3 V.
Upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the transmit and
receive delay lines and lock the Phase Lock Loop to the receive line. A reference clock is required
to calibrate the delay lines. The transmitter reference is provided by TCLK. The crystal oscillator
provides the receiver reference. If the crystal oscillator is grounded, MCLK is used as the receiver
reference clock.
The transceiver can also be reset from the Host or Hardware mode. In Host mode, reset is
commanded by simultaneously writing ones to RLOOP and LLOOP, and a zero to TAOS. In
Hardware mode, reset is commanded by holding RLOOP and LLOOP High simultaneously for 200
ns while holding TAOS Low. In either mode, reset clears and sets all registers to 0.
Receiver
The twisted-pair input is received via a 1:1 transformer. Recovered data is output at RPOS/RNEG
(RDATA in unipolar mode), and the recovered clock is output at RCLK. Refer to Test
Specifications for receiver timing.
The signal received at RPOS and RNEG is processed through the receive equalizer. The Equalizer
Gain Limit (EGL) input determines the maximum gain that may be applied at the equalizer. When
set Low, up to 36 dB of gain may be applied.
When EGL is High, gain is limited to no more than 26 dB providing for increased noise margin in
shorter loop operation. Insertion loss of the line in 7.5 dB steps, as indicated by the receive
equalizer setting, is encoded in the LATN output as shown in
T1 CSU/ISDN PRI Transceiver — LXT310
Figure
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