PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet
PDLXT310NE.D4
Specifications of PDLXT310NE.D4
Related parts for PDLXT310NE.D4
PDLXT310NE.D4 Summary of contents
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LXT310 T1 CSU/ISDN PRI Transceiver The LXT310 is the first fully integrated transceiver for T1 CSU and ISDN Primary Rate Interface (ISDN PRI) applications at 1.544 Mbps. This transceiver operates over 6,000 feet of 22 AWG twisted-pair cable without any ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Contents 1.0 Pin Assignments and Signal Descriptions 2.0 Functional Description 2.1 Power Requirements............................................................................................. 9 2.1.1 Initialization and Reset Operations........................................................... 9 2.2 Receiver ................................................................................................................ 9 2.3 Transmitter ..........................................................................................................10 2.3.1 Idle Mode................................................................................................10 2.3.2 Short Circuit Limit ...................................................................................11 2.3.3 Line Code ...............................................................................................11 2.4 ...
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LXT310 — T1 CSU/ISDN PRI Transceiver Figures 1 LXT310 Block Diagram ......................................................................................... 5 2 LXT310 Pin Assignments and Package Markings ................................................ 6 3 LATN Pulse Width Encoding............................................................................... 10 4 50% AMI Coding ................................................................................................. 11 5 LXT310 Serial Interface Data Structure ...
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Figure 1. LXT310 Block Diagram TCLK B8ZS/ TPOS Unipolar TNEG Encoder Encoder Enable RLOOP Enable XTAL IN Jitter Attenuator XTAL OUT JASEL Decoder Remote Enable Loopback B8ZS/ RPOS Unipolar RNEG Decoder RCLK NLOOP Inband NLOOP & INT LOS Processor LOS ...
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LXT310 — T1 CSU/ISDN PRI Transceiver 1.0 Pin Assignments and Signal Descriptions Figure 2. LXT310 Pin Assignments and Package Markings 1 28 MCLK 2 27 TCLK TPOS / TDATA 3 26 TNEG / UBS 4 25 MODE 5 24 RNEG ...
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Table 1. Pin Descriptions Pin # Sym I/O Master Clock. A 1.544 MHz clock input used to generate internal clocks. Upon Loss of 1 MCLK I Signal (LOS), RCLK is derived from MCLK. If MCLK is not applied, this pin ...
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LXT310 — T1 CSU/ISDN PRI Transceiver Table 1. Pin Descriptions (Continued) Pin # Sym I/O 19 RTIP I Receive Tip; Receive Ring. The AMI signal received from the line is applied at these pins. A 1:1 transformer is required. Data ...
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Functional Description The LXT310 is a fully integrated PCM transceiver for 1.544 Mbps (T1) applications. It allows full-duplex transmission of digital data over existing twisted-pair installations. The LXT310 interfaces with two twisted-pair lines (one pair for transmit, one pair ...
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LXT310 — T1 CSU/ISDN PRI Transceiver Figure 3. LATN Pulse Width Encoding RCLK LATN 1 2 LATN = 2 RCLK Attenuation LATN = 1 RCLK, 7 Attenuation NOTE: LATN is stable and valid on the ...
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The transmitted pulse shape is determined by Line Build Out (LBO) inputs LBO1 and LBO2 as follows: Line Build-Out Control LBO1 LBO2 In Host mode, LBO is specified by setting the appropriate bits in the LXT310 register via the serial ...
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LXT310 — T1 CSU/ISDN PRI Transceiver Data (TPOS/TNEG / TDATA or RPOS/RNEG / RDATA) is clocked into the ES with the associated clock signal (TCLK or RCLK), and clocked out of the ES with the dejittered clock from the JAL. ...
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Figure 5. LXT310 Serial Interface Data Structure CS SCLK ADDRESS / COMMAND BYTE R SDI/ SDO 0 0 ADDRESS / R/W COMMAND A0 BYTE CLEAR INTERRUPTS INPUT DATA LOS NLOOP D0 (LSB) BYTE 1=ENABLE . Table 3. ...
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LXT310 — T1 CSU/ISDN PRI Transceiver 2.5.3 Diagnostic Mode Operation 2.5.3.1 Transmit All Ones In Transmit All Ones (TAOS) mode, the TPOS and TNEG inputs to the transceiver are ignored and the transceiver transmits a continuous stream of ones at ...
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... CTS Knights (6.176 MHz) 1 Valpey Fisher U.S. Crystal 1. The customer should always verify the specifications of the quartz crystal against Intel’s recommended specification point- by-point to make certain that the crystal suits the desired application. Datasheet T1 CSU/ISDN PRI Transceiver — LXT310 Figure 6 Table 5 lists approved crystals and transformers ...
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... Rx Transformer Pulse Engineering (1: 1) Schott Corp HALO 1. The customer should always verify the specifications of the quartz crystal against Intel’s recommended specification point- by-point to make certain that the crystal suits the desired application. 3.1.1 Host Mode Applications Figure 7 shows a typical T1 CSU application with the LXT310 operating in the Host mode (MODE pin tied high) ...
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Table 6. LXT310 Crystal Specifications (External) Parameter Maximum drive level Mode of operation Crystal holder Datasheet T1 CSU/ISDN PRI Transceiver — LXT310 Specification 2.0 mW Fundamental HC49 (R3W maximum typical M ...
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LXT310 — T1 CSU/ISDN PRI Transceiver Figure 7. Typical LXT310 Host Mode T1/CSU Application See Note 1 T1/ESF FRAMER FSYNC TMSYNC TCLK CS TPOS SDO TNEG SDI SPS INT RNEG SCLK RPOS RCLK LXP600A CLAD CLKI FSI CLKO 2.048 MHz ...
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LBO, and the EGL pin is tied low, allowing for full receiver gain. The TAOS, LLOOP and RLOOP diagnostic modes are individually controllable. The RCLK input to the OR gate at RLOOP allows for clocking of ...
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LXT310 — T1 CSU/ISDN PRI Transceiver 4.0 Test Specifications Note: The minimum and maximum values in represent the performance specifications of the LXT310 and are guaranteed by test, except where noted by design Table 7. Absolute Maximum Ratings Parameter DC ...
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Table 10. Analog Characteristics (Under Recommended Operating Conditions) Parameter Recommended output load at TTIP and TRING AMI Output Pulse Amplitudes kHz 8 kHz - 40 kHz kHz 2 Jitter added by the ...
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LXT310 — T1 CSU/ISDN PRI Transceiver Table 11. Pulse Mask Corner Point Specifications Maximum Curve Time (ns) 425 500 675 725 1100 1250 Table 12. LXT310 Receive Timing Characteristics (See Figure 10) Parameter 2 Receive clock duty cycle Receive clock ...
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Table 13. LXT310 Master Clock and Transmit Timing Characteristics (See Figure 11) Parameter Master clock frequency Master clock tolerance Master clock duty cycle Crystal frequency Transmit clock frequency Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG to TCLK setup time ...
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LXT310 — T1 CSU/ISDN PRI Transceiver Figure 12. LXT310 Serial Data Input Timing Diagram SCLK t DC LSB SDI Control Byte Figure 13. LXT310 Serial Data Output Timing Diagram CS SCLK t CDV SDO CLKE=1 ...
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Mechanical Specification Figure 14. Package Specifications 28-pin Plastic Dual In-Line Package • P/N LXT310NE • Temperature Range - ° 28-pin Plastic Leaded Chip Carrier • P/N LXT310PE • Temperature Range -40 ...
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