PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet - Page 203

• Manufacturer Part Number: PSB21150HV14XP
• Manufacturer: Lantiq

Specifications of PSB21150HV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

XXX_
TSDPxy
4.4.2
Register
CDA_TSDP10
CDA_TSDP11
CDA_TSDP20
CDA_TSDP21
BCHA_TSDP_BC1 48
BCHA_TSDP_BC2 49
BCHB_TSDP_BC1 4A
BCHB_TSDP_BC2 4B
TR_TSDP_BC1
TR_TSDP_BC2
This register determines the time slots and the data ports on the IOM-2 interface for the
data channels ’xy’ of the functional units ’XXX’ which are Controller Data Access (CDA),
B-channel controllers (BCHA, BCHB) and Transceiver (TR).
Each of the two B-channel controllers (BCHA, BCHB) can access any combination of
two 8-bit timeslots and one 2-bit timeslot (e.g. 16-bit access to B1+B2 or 18-bit IDSL in
2B+D). The position of the two 8-bit timeslots is programmed in BCHx_TSDP_BC1 and
BCHx_TSDP_BC2. The position of the 2-bit timeslot is programmed in BCHA_CR and
BCHB_CR. In the same registers each of the three timeslots is enabled/disabled.
The position of B-channel data from the S-interface is programmed in TR_TSDP_BC1
and TR_TSDP_BC2.
Note: The reset values for TR_TSDP_BC1/2 are depending on the mode selection
Data Sheet
(MODE0/1) and channel selection (CH0-2).
7
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy
DPS
Register
Address
44
45
46
47
4C
4D
0
H
H
H
H
H
H
H
H
H
H
0
Value after Reset
00
01
80
81
80
81
81
85
00
01
203
H
H
H
H
H
H
H
H
H
H
( = output on B1-DD)
( = output on B2-DD)
( = output on B1-DU)
( = output on B2-DU)
( = output on B1-DU)
( = output on B2-DU)
( = output on B2-DU)
( = output on IC2-DU)
( = transceiver output on B1-DD), see note
( = transceiver output on B2-DD), see note
TSS
Detailed Register Description
0
PSB/PSF 21150
2003-01-30
IPAC-X
RD/WR
(44-4D)