PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet - Page 156

• Manufacturer Part Number: PSB21150HV14XP
• Manufacturer: Lantiq

Specifications of PSB21150HV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

IPAC-X
PSB/PSF 21150
Description of Functional Blocks
are still a maximum of 48 bytes (64 bytes - 16 bytes) to be transmitted. With a 32 bytes
block size (D- or B-channel) the XPR is initiated when a transmit FIFO space of at least
32 bytes is available to accept further data, i.e. there are still a maximum of 32 bytes (D-
channel: 64 bytes - 32 bytes) or 96 bytes (B-channel: 128 bytes - 32 bytes) to be
transmitted. The maximum reaction time for the smaller block size is 50 % higher with
the trade-off of a doubled interrupt load. With a selected block size an XPR always
indicates the available space in the XFIFOx, so any number of bytes smaller than the
selected XFBS may be stored in the FIFO during one “write block“ access cycle.
Similar to RFBS for the receive FIFO, a new setting of XFBS takes effect after the next
XTF,XME or XRES command. XRES resets the XFIFOx.
The XFIFOx can hold any number of frames fitting in the 64 bytes (D-channel) or 128
bytes (B-channel), respectively.
Possible Error Conditions During Transmission of Frames
If the transmitter sees an empty FIFO, i.e. if the microcontroller doesn’t react fast enough
to an XPR interrupt, an XDU (transmit data underrun) interrupt will be generated. If the
HDLC channel becomes unavailable during transmission the transmitter tries to repeat
the current frame as specified in the LAPD protocol. This is impossible after the first data
block has been sent (16 or 32 bytes for D-channel; 32 or 64 byte for B-channel), in this
case an XMR transmit message repeat interrupt is set and the microcontroller has to
send the whole frame again.
Both XMR and XDU interrupts cause a reset of the XFIFOx. The XFIFOx is locked while
an XMR or XDU interrupt is pending, i.e. all write actions of the microcontroller will be
ignored as long as the microcontroller hasn’t read the ISTAx register with the set XDU,
XMR interrupts.
If the microcontroller writes more data than allowed (block size), then the data in the
XFIFOx will be corrupted and the STARx.XDOV bit is set. If this happens, the
microcontroller has to abort the transmission by CMDRx.XRES and start new.
The general procedures for a data transmission sequence are outlined in the flow
diagram in
Figure
83.
Data Sheet
156
2003-01-30