ISPPAC-POWR604-01T44I Lattice, ISPPAC-POWR604-01T44I Datasheet - Page 11

• Manufacturer Part Number: ISPPAC-POWR604-01T44I
• Description: Supervisory Circuits 5V 8 Macro Cell
• Manufacturer: Lattice

Specifications of ISPPAC-POWR604-01T44I

• Number Of Voltages Monitored: 6
• Monitored Voltage: Adjustable
• Undervoltage Threshold: 1.03 V
• Overvoltage Threshold: 5.72 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current (typ): 10000 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2. Voltage Monitors
Each monitor consists of three major subsystems. The core of the monitor is a voltage comparator. This compara-
tor outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than that at its negative
terminal, otherwise it outputs a LOW signal. A small amount of hysteresis is provided by the comparator to reduce
the effects of input noise.
The input signal is attenuated by a programmable resistive divider before it is fed into the comparator. This feature
is used to determine the coarse range in which the comparator should trip (e.g. 1.8V, 3.3V, 5V). Twelve possible
ranges are available from the input divider network. The comparator’s negative terminal is obtained from a pro-
grammable reference source (Reference), which may be set to one of 16 possible values scaled in approximately
1% increments from each other, allowing for fine tuning of the voltage monitor’s trip points. This combination of
coarse and fine adjustment supports 192 possible trip-point voltages for a given monitor circuit. Because each
monitor’s reference and input divider settings are completely independent of those of the other monitor circuits, the
user can set any input monitor to any of the 192 available settings.
Comparator Hysteresis
PLD Architecture
The ispPAC-POWR604 digital logic is composed of an internal PLD that is programmed to perform the sequencing
functions. The PLD architecture allows flexibility in designing various state machines and control logic used for
monitoring. The macrocell shown in Figure 3 is the heart of the PLD. There are eight macrocells that can be used to
1. The hysteresis scales depending on the voltage monitor range that is selected. The values show are typical and
VMON1..VMON6
are centered around the nominal voltage trip point for a given range selection.
Monitor Voltage
Range Setting
V
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
MON
1
Typical Hysteresis on
Over Voltage Range
+/- 16.2
+/- 10.7
+/- 8.1
+/- 5.8
+/- 4.9
+/- 3.9
11
Reference
Typical Hysteresis on
Under Voltage Range
+/- 14.0
+/- 9.2
+/- 7.0
+/- 5.0
+/- 4.2
+/- 3.4
ispPAC-POWR604 Data Sheet
Hysteresis
3mV
To PLD Array
Units
mV
mV
mV
mV
mV
mV