71M6542F-IGT/F Maxim Integrated Products, 71M6542F-IGT/F Datasheet - Page 89

• Manufacturer Part Number: 71M6542F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6542F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

v1.1
WF_BADVDD
WF_CSTART
WAKE_ARM
WF_RSTBIT
EW_DIO52
EW_DIO55
WF_DIO52
WF_DIO55
EW_DIO4
WF_DIO4
WF_ERST
WF_TMR
WF_RST
EW_PB
EW_RX
WF_PB
WF_RX
Name
Location
28B3[2]
28B3[1]
28B3[0]
28B2[5]
28B3[3]
28B3[4]
28B1[2]
28B1[1]
28B1[0]
28B1[5]
28B1[3]
28B1[4]
28B0[6]
28B0[5]
28B0[3]
28B0[7]
28B0[2]
© 2008–2011 Teridian Semiconductor Corporation
RST
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
WK
–
–
–
–
–
–
–
–
–
–
–
–
–
R/W
R/W
R/W
R/W
R/W
R/W
Table 70: Wake Bits
Dir
R
R
R
R
R
R
R
Description
Connects SEGDIO4 to the WAKE logic and permits
SEGDIO4 rising to wake the part. This bit has no effect
unless SEGDIO4 is configured as a digital input.
Connects DIO52 to the WAKE logic and permits DIO52
high-level to wake the part (71M6542F only). This bit
has no effect unless DIO52 is configured as a digital
input.
Connects DIO55 to the WAKE logic and permits DIO55
high-level to wake the part. This bit has no effect unless
DIO55 is configured as a digital input.
Arms the WAKE timer and loads it with the value in the
WAKE_TMR register (I/O RAM 0x2880). When SLP
mode or LCD mode is asserted by the MPU, the WAKE
timer becomes active.
Connects the PB pin to the WAKE logic and permits PB
high-level to wake the part. PB is always configured as
an input.
Connects the RX pin to the WAKE logic and permits RX
rising to wake the part. See
SEGDIO4 flag bit. If SEGDIO4 is configured to wake
the part, this bit is set whenever SEGDIO4 rises. It is
held in reset if SEGDIO4 is not configured for wakeup.
SEGDIO52 flag bit. If SEGDIO52 is configured to wake
the part, this bit is set whenever SEGDIO52 is a high
level. It is held in reset if SEGDIO52 is not configured
for wakeup (71M6542F only).
SEGDIO55 flag bit. If SEGDIO55 is configured to wake
the part, this bit is set whenever SEGDIO55 is a high
level. It is held in reset if SEGDIO55 is not configured
for wakeup.
Indicates that the Wake timer caused the part to wake up.
Indicates that the PB pin caused the part to wake.
Indicates that RX pin caused the part to wake.
Indicates that the RST pin, E_RST pin, RESET bit (I/O
RAM 0x2200[3]), the cold start detector, or low voltage
on the VBAT pin caused the part to reset.
*See
Table 71
for details.
3.4.1
for de-bounce issues.
89