71M6542F-IGT/F Maxim Integrated Products, 71M6542F-IGT/F Datasheet - Page 82

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71M6542F-IGT/F

Manufacturer Part Number
71M6542F-IGT/F
Description
PMIC Solutions Precision Energy Meter IC
Manufacturer
Maxim Integrated Products
Type
Metering SoCr
Datasheet

Specifications of 71M6542F-IGT/F

Core
8051
Core Architecture
8051
Data Bus Width
8 bit
Data Ram Size
5 KB
Device Million Instructions Per Second
5 MIPS
Interface Type
I2C, ICE, SPI, UART
Maximum Clock Frequency
5 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Programmable I/os
51
Number Of Timers
2
On-chip Adc
22 bit
Operating Supply Voltage
3 V to 3.6 V
Package / Case
LQFP-100
Processor Series
8051
Program Memory Size
64 KB
Program Memory Type
Flash
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
71M6542F-IGT/F
Manufacturer:
AD
Quantity:
1 500
The MPU has access to a variety of registers that signal the event that caused the wake up. See
Wake Up Behavior
Table 67
Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events:
CE (Computation Engine)
FIR
ADC, VREF
PLL
Battery Measurement
Temperature sensor
Max MPU clock rate
MPU_DIV clk. divider
ICE
DIO Pins
Watchdog Timer
LCD
LCD Boost
EEPROM Interface (2-wire)
EEPROM Interface (3-wire)
UART (full speed)
Optical TX modulation
Flash Read
Flash Page Erase
Flash Write
RAM Read and Write
Wakeup Timer
OSC and RTC
DRAM data preservation
NV RAM data preservation
Notes:
82
Circuit Function
Wake-up timer timeout.
Pushbutton (PB) is activated.
A rising edge on SEGDIO4, SEGDIO52 (71M6542F only) or SEGDIO55.
Activity on the RX or OPT_RX pins.
1.
2.
3.
The CE is active in BRN mode, but ADC data is inaccurate. The MPU should halt the CE to conserve power (CE_E = 0,
I/O RAM 0x2106[0]).
“--“ indicates that the corresponding circuit is not active
“Boost” implies that the LCD boost circuit is active (i.e., LCD_VMODE[1:0] = 10 (I/O RAM 0x2401[7:6]). The LCD boost
circuit requires a clock from the PLL to function. Thus, the PLL is automatically kept active if LCD boost is active while in
LCD mode, otherwise the PLL is de-activated.
shows the circuit functions available in each operating mode.
for details.
PLL_FAST=1
(from PLL)
© 2008–2011 Teridian Semiconductor Corporation
4.92MHz
38.4kHz
MSN (Mission Mode)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
System Power
Table 67: Available Circuit Functions
PLL_FAST=0
(from PLL)
1.57MHz
38.9kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PLL_FAST=1
(from PLL)
BRN (Brownout Mode)
4.92MHz
38.4kHz
Note 1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
--
--
Battery Power
PLL_FAST=0
(from PLL)
1.57MHz
38.9kHz
Note 1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
--
--
Boost
LCD
Yes
Yes
Yes
Yes
Yes
Yes
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
2
2
3.4
SLEEP
Yes
Yes
Yes
Yes
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
v1.1

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