MAX5062DASA-T Maxim Integrated Products, MAX5062DASA-T Datasheet - Page 11

• Manufacturer Part Number: MAX5062DASA-T
• Description: MOSFET & Power Driver ICs 125V 2A Half-Bridge MOSFET Driver
• Manufacturer: Maxim Integrated Products
• Type: High Side/Low Sider

Specifications of MAX5062DASA-T

• Rise Time: 65 ns
• Fall Time: 65 ns
• Supply Voltage (min): 8 V
• Supply Current: 3 mA
• Maximum Power Dissipation: 1538.5 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Bridge Type: Half Bridge
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 2
• Number Of Outputs: 2

Topologies like the two-switch forward converter, where
both high- and low-side switches are turned on and off
simultaneously, can have the BBM function disabled by
leaving BBM unconnected. When disabled, t
cally 1ns.
The MAX5062_/MAX5064A are CMOS (V
input drivers while the MAX5063_/MAX5064B have TTL-
compatible logic inputs. The logic-input signals are
independent of V
ered by a 10V supply while the logic inputs are provid-
ed from a 12V CMOS logic. Also, the logic inputs are
protected against voltage spikes up to 15V, regardless
of the V
have 400mV and 1.6V hysteresis, respectively, to avoid
double pulsing during transition. The logic inputs are
high-impedance pins and should not be left floating.
The low 2.5pF input capacitance reduces loading and
increases switching speed. The noninverting inputs are
pulled down to GND and the inverting inputs are pulled
up to V
output from the controller must assume a proper state
while powering up the device. With the logic inputs
floating, the DH and DL outputs pull low as V
up above the UVLO threshold.
The MAX5064_ has two logic inputs per driver, which
provide greater flexibility in controlling the MOSFET.
Use IN_H+/IN_L+ for noninverting logic and IN_H-/
IN_L- for inverting logic operation. Connect
IN_H+/IN_L+ to V
used. Alternatively, the unused input can be used as an
ON/OFF function. Use IN_+ for active-low and IN_- for
active-high shutdown logic.
Table 1. MAX5064_ Truth Table
The MAX5062/MAX5063/MAX5064 uses a single-shot
level shifter architecture to achieve low propagation
delay. Typical level shifter architecture causes a mini-
mum (high or low) pulse width (t
may be higher than the logic-input pulse width. For
MAX5062/MAX5063/MAX5064 devices, the DH mini-
mum high pulse width (t
minimum low pulse width (t
IN_H+/IN_L+
Driver Logic Inputs (IN_H, IN_L, IN_H+,
High
High
Low
Low
DD
DD
internally using a 1MΩ resistor. The PWM
voltage. The TTL and CMOS logic inputs
DD
______________________________________________________________________________________
DD
. For example, the IC can be pow-
IN_H-/IN_L-
and IN_H-/IN_L- to GND if not
DMIN-DH-H
High
High
Low
Low
Minimum Pulse Width
DMIN-DL-L
IN_H-, IN_L+, IN_L-)
DMIN
) is lower than the DL
) at the output that
) to avoid any
DD
BBM
DH/DL
High
Low
Low
Low
/ 2) logic-
DD
Half-Bridge MOSFET Drivers
is typi-
rises
shoot-through in the absence of external BBM delay
during the narrow pulse at low duty cycle (see Figure 2).
At high duty cycle (close to 100%) the DH minimum low
pulse width (t
minimum low pulse width (t
and shoot-through (see Figure 3). In the case of
MAX5062/MAX5063/MAX5064, there is a possibility of
about 40ns overlap if an external BBM delay is not pro-
vided. We recommend adding external delay in the INH
path so that the minimum low pulse width seen at INH
is always longer than t
Characteristics table for the typical values of t
Figure 2. Minimum Pulse-Width Behavior for Narrow Duty-
Cycle Input (On-Time < t
A)
B)
125V/2A, High-Speed,
PWM
PWM
DH
DL
MAX5062B/MAX5062D/MAX5063B/MAX5063D/MAX5064
IN
IN
V
DD
DMIN-DH-L
INH
INL
PW-MIN
t
DMIN-DH-H
) must be higher than the DL
t
DMIN-DL-L
PW-MIN
DMIN-DL-L
)
DH
HS
DL
. See the Electrical
V
IN
N
N
) to avoid overlap
BUILT-IN
DEAD TIME
PW-MIN
V
OUT
.
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