WM8311GEB/V Wolfson Microelectronics, WM8311GEB/V Datasheet - Page 38

• Manufacturer Part Number: WM8311GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 121BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8311GEB/V

• Supply Voltage: 5.5V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 7
• Digital Ic Case Style: BGA
• No. Of Pins: 121
• No. Of Regulated Outputs: 9
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

WM8311
11.7 RESET PIN FUNCTION
w
R16401
(4011h)
Interrupt Status
1
R16409
(4019h)
Interrupt Status
1 Mask
Table 6 ON Pin Interrupt
The RESET
WM8311 and in other connected devices. The pin is an open-drain type, and can be driven low by
external sources or by the WM8311 itself.
The WM8311 drives the RESET
SLEEP is configurable; this is determined by the RST_SLPENA register bit as defined in Table 7.
The WM8311 clears the RESET
transition, the RESET
duration. The RESET
details.
The WM8311 detects a Hardware Reset request whenever the RESET
external source. In this event, the WM8311 resets the internal control registers (excluding the RTC)
and initiates a start-up sequence. See Section 24.
It is possible to mask the RESET
bit. In SLEEP mode, if RST_SLP_MSK is set, the WM8311 will take no action if the RESET
pulled low.
Note that the RESET
only be changed by writing the appropriate code to the Security register, as described in
Section 12.4.
R16390 (4006h)
Reset Control
Table 7 RESET Pin Control Registers
ADDRESS
ADDRESS
¯ ¯ ¯ ¯ ¯ ¯ pin is an active low input/output which is used to command Hardware Resets in the
¯ ¯ ¯ ¯ ¯ ¯ pin control registers are locked by the WM8311 User Key. These registers can
¯ ¯ ¯ ¯ ¯ ¯ delay period is set by the RST_DUR register bit. See Figure 6 for further
¯ ¯ ¯ ¯ ¯ ¯ pin is held low for a further delay time period, extending the RESET
BIT
12
12
BIT
1:0
5
4
¯ ¯ ¯ ¯ ¯ ¯ pin input in the SLEEP state by setting the RST_SLP_MSK register
¯ ¯ ¯ ¯ ¯ ¯ pin low in the OFF state. The output status of the RESET
¯ ¯ ¯ ¯ ¯ ¯ pin following the transition to ON. On completion of the state
ON_PIN_CINT
IM_ON_PIN_CINT
RST_SLP_MSK
RST_SLPENA
RST_DUR
LABEL
LABEL
DEFAULT
11
1
1
ON pin interrupt.
(Rising and Falling Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Masks the RESET
SLEEP mode
0 = External RESET
1 = External RESET
SLEEP
Protected by user key
Sets the output status of RESET
in SLEEP
0 = RESET
1 = RESET
Protected by user key
Delay period for releasing RESET
after ON or WAKE sequence
00 = 1ms
01 = 10ms
10 = 50ms
11 = 100ms
Protected by user key
¯ ¯ ¯ ¯ ¯ ¯ high (not asserted)
¯ ¯ ¯ ¯ ¯ ¯ low (asserted)
¯ ¯ ¯ ¯ ¯ ¯ pin is driven low by an
PP, December 2009, Rev 3.0
DESCRIPTION
DESCRIPTION
¯ ¯ ¯ ¯ ¯ ¯ pin input in
¯ ¯ ¯ ¯ ¯ ¯ active in SLEEP
¯ ¯ ¯ ¯ ¯ ¯ masked in
Pre-Production
¯ ¯ ¯ ¯ ¯ ¯ pin in
¯ ¯ ¯ ¯ ¯ ¯ pin is
¯ ¯ ¯ ¯ ¯ ¯ pin
¯ ¯ ¯ ¯ ¯ ¯
¯ ¯ ¯ ¯ ¯ ¯ low
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