PIC24FJ128DA110-I/PT Microchip Technology Inc., PIC24FJ128DA110-I/PT Datasheet - Page 319

• Manufacturer Part Number: PIC24FJ128DA110-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 128KB Flash, 24K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ128DA110-I/PT

• A/d Inputs: 24 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 100-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 24K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 22-25: G1CLUT: COLOR LOOK-UP TABLE CONTROL REGISTER
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-10
bit 9
bit 8
bit 7-0
CLUTADR7
CLUTEN
R/W-0
R/W-0
CLUTEN: Color Look-up Table Enable Control bit
1 = Color look-up table is enabled
0 = Color look-up table is disabled
CLUTBUSY: Color Look-up Table Busy Status bit
1 = A CLUT entry read/write access is being executed
0 = No CLUT entry read/write access is being executed
Unimplemented: Read as ‘0’
CLUTTRD: Color Look-up Table Read Trigger bit
Enabling this bit will trigger a read to the CLUT location determined by the CLUTADR bits
(G1CLUT<7:0>) with CLUTRWEN enabled.
1 = CLUT read trigger is enabled (must be cleared in software after reading data in the G1CLUTRD
0 = CLUT read trigger is disabled
CLUTRWEN: Color Look-up Table Read/Write Enable Control bit
This bit must be set when reading or modifying entries on the CLUT and it must also be cleared when
CLUT is used by the display controller.
1 = Color look-up table read/write enabled; display controller cannot access the CLUT
0 = Color look-up table read/write disabled; display controller can access the CLUT
CLUTADR<7:0>: Color Look-up Table Memory Address bits
CLUTBUSY
CLUTADR6
R-0, HSC
R/W-0
register)
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
CLUTADR5 CLUTADR4 CLUTADR3 CLUTADR2 CLUTADR1
R/W-0
U-0
—
PIC24FJ256DA210 FAMILY
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
R/W-0
U-0
—
x = Bit is unknown
CLUTTRD
R/W-0
R/W-0
DS39969B-page 319
CLUTRWEN
CLUTADR0
R/W-0
R/W-0
bit 8
bit 0