ISP1506ABS-T ST-Ericsson Inc, ISP1506ABS-T Datasheet - Page 7

• Manufacturer Part Number: ISP1506ABS-T
• Description: IC USB TXRX HS 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1506ABS-T

• Number Of Drivers/receivers: 1/1
• Protocol: USB 2.0
• Voltage - Supply: 1.65 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
7. Functional description
ISP1506A_ISP1506B_1
Product data sheet
7.1 ULPI interface controller
7.2 USB serializer and deserializer
7.3 Hi-Speed USB (USB 2.0) ATX
The ISP1506 provides an 8-pin interface that is compliant with
Interface (ULPI) Specification Rev.
The ULPI interface controller provides the following functions:
For more information on the ULPI protocol, see
The USB data serializer prepares data to transmit on the USB bus. To transmit data, the
USB link sends a transmit command and data on the ULPI bus. The serializer performs
parallel-to-serial conversion, bit stuffing and NRZI encoding. For packets with a PID, the
serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end
of the packet. When the serializer is busy and cannot accept any more data, the ULPI
interface controller de-asserts NXT.
The USB data deserializer decodes data received from the USB bus. When data is
received, the deserializer strips the SYNC and EOP patterns, and then performs
serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data
payload. The ULPI interface controller sends data to the USB link by asserting DIR, and
then asserting NXT whenever a byte is ready. The deserializer also detects various
receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and
byte-alignment errors.
The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to
transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for
USB peripheral, host and OTG implementations. The following circuitry is included:
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ULPI-compliant interface and register set
Allows full control over the USB peripheral, host and OTG functionality
Parses the USB transmit and receive data
Prioritizes the USB receive data, USB transmit data, interrupts and register operations
Control of the V
V
Low-power mode
3-pin serial mode
Generates RXCMDs (status updates)
Maskable interrupts
Control over the ULPI bus state; can attach weak pull-down resistors to DATA[3:0]
Differential drivers to transmit data at high-speed, full-speed and low-speed
Differential and single-ended receivers to receive data at high-speed, full-speed and
low-speed
BUS
monitoring, charging and discharging
BUS
Rev. 01 — 30 May 2007
charge pump or external source
1.1”. This interface must be connected to the USB link.
ISP1506A; ISP1506B
Section
9.
ULPI HS USB OTG transceiver
Ref. 3 “UTMI+ Low Pin
© NXP B.V. 2007. All rights reserved.
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