DSPIC30F4011-30I/P Microchip Technology Inc., DSPIC30F4011-30I/P Datasheet - Page 117

• Manufacturer Part Number: DSPIC30F4011-30I/P
• Description: 16 BIT MCU/DSP 40LD 30MIPS 48 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F4011-30I/P

• A/d Inputs: 9-Channels, 10-Bit
• Comparators: 4
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: CAN, I2C/SPI/UART, USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 40-pin PDIP
• Programmable Memory: 48K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard, with a 16-bit interface.
This module offers the following key features:
• I
• I
• I
• I
• Serial clock synchronization for I
• I
FIGURE 17-1:
17.1.3
I2CCON and I2CSTAT are control and status registers,
respectively. The I2CCON register is readable and writ-
able. The lower 6 bits of I2CSTAT are read only. The
remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer, as shown in Figure 16-1.
I2CTRN is the transmit register to which bytes are writ-
ten during a transmit operation, as shown in Figure 16-2.
 2004 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046).
operation.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and will arbitrate accordingly.
2
2
2
2
2
C interface supporting both Master and Slave
C Slave mode supports 7 and 10-bit address.
C Master mode supports 7 and 10-bit address.
C port allows bi-directional transfers between
C supports Multi-Master operation; detects bus
I
2
C MODULE
I
2
C REGISTERS
PROGRAMMER’S MODEL
bit 15
bit 15
2
C serial communication
2
C) module provides
2
C port can be
bit 9
bit 8
bit 7
bit 7
Preliminary
17.1
The hardware fully implements all the master and slave
functions of the I
tions, as well as 7 and 10-bit addressing.
Thus, the I
a master on an I
17.1.1
The following types of I
• I
• I
• I
See the I
17.1.2
I
is data.
The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the baud rate generator reload value.
In receive operations, I2CRSR and I2CRCV to-
gether form
I2CRSR receives a complete byte, it is transferred to
I2CRCV and an interrupt pulse is generated. During
transmission, the I2CTRN is not double buffered.
2
C has a 2-pin interface; pin SCL is clock and pin SDA
Note:
2
2
2
C Slave operation with 7-bit address
C Slave operation with 10-bit address
C Master operation with 7 or 10-bit address
Operating Function Description
2
C programmer’s model in Figure 17-1.
2
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
C module can operate either as a slave or
VARIOUS I
PIN CONFIGURATION IN I
Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
a
2
2
C bus.
C Standard and Fast mode specifica-
double
I2CRCV (8 bits)
I2CTRN (8 bits)
I2CBRG (9 bits)
I2CCON (16-bits)
I2CSTAT (16-bits)
I2CADD (10-bits)
2
C operation are supported:
2
C MODES
buffered
dsPIC30F
DS70082G-page 115
receiver.
2
C MODE
When