PIC24HJ128GP510-I/PT Microchip Technology Inc., PIC24HJ128GP510-I/PT Datasheet - Page 158
PIC24HJ128GP510-I/PT
Manufacturer Part Number
PIC24HJ128GP510-I/PT
Description
MCU, 16-Bit, 128KB Flash, 8KB RAM, 85 I/O, TQFP-100
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC24HJ128GP510-IPT.pdf
(286 pages)
Specifications of PIC24HJ128GP510-I/PT
A/d Inputs
32 Channel, 12-Bit
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
85
Interface
CAN/I2C/SPI/UART
Memory Type
Flash
Number Of Bits
16
Number Of Inputs
85
Number Of Pins
100
Package Type
100-pin TQFP
Programmable Memory
128K Bytes
Ram Size
8K Bytes
Speed
40 MIPS
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6 V
Voltage, Rating
3-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC24HJXXXGPX06/X08/X10
16.11 Slope Control
The I
and SCLx signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user to disable slew rate con-
trol if desired. It is necessary to disable the slew rate
control for 1 MHz mode.
16.12 Clock Arbitration
Clock arbitration occurs when the master deasserts the
SCLx pin (SCLx allowed to float high) during any
receive, transmit or Restart/Stop condition. When the
SCLx pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the
SCLx pin is actually sampled high. When the SCLx pin
is sampled high, the Baud Rate Generator is reloaded
with the contents of I2CxBRG and begins counting.
This ensures that the SCLx high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device.
DS70175F-page 156
2
C standard requires slope control on the SDAx
16.13 Multi-Master Communication, Bus
Multi-Master mode support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDAx pin, arbitration takes place when the
master outputs a ‘1’ on SDAx by letting SDAx float high
while another master asserts a ‘0’. When the SCLx pin
floats high, data should be stable. If the expected data
on SDAx is a ‘1’ and the data sampled on the
SDAx pin = 0, then a bus collision has taken place. The
master will set the I
reset the master portion of the I
Collision and Bus Arbitration
2
C master events interrupt flag and
© 2007 Microchip Technology Inc.
2
C port to its Idle state.
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