PIC16LF1826-I/ML Microchip Technology Inc., PIC16LF1826-I/ML Datasheet - Page 278
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC16LF1826-I/ML
Manufacturer Part Number
PIC16LF1826-I/ML
Description
3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, n
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16LF1826-I/ML
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin QFN
Programmable Memory
3.5K Bytes
Ram Size
256 Bytes
Speed
32 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16(L)F1826/27
25.7
The MSSPx module has a Baud Rate Generator avail-
able for clock generation in both I
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPxADD register
When a write occurs to SSPxBUF, the Baud Rate Gen-
erator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
FIGURE 25-40:
TABLE 25-4:
DS41391D-page 278
Note 1:
Note: Values of 0x00, 0x01 and 0x02 are not valid
BAUD RATE GENERATOR
for SSPxADD when used as a Baud Rate
Generator for I
limitation.
32 MHz
32 MHz
32 MHz
16 MHz
16 MHz
16 MHz
4 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
F
OSC
2
C interface does not conform to the 400 kHz I
MSSPX CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C. This is an implementation
SSPxM<3:0>
Figure 25-39
SCLx
2
C and SPI Master
(Register
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
1 MHz
SSPxM<3:0>
F
triggers the
CY
Control
Reload
25-6).
SSPxCLK
Reload
2
module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSPx is
being operated in.
Table 25-4
instruction cycles and the BRG value loaded into
SSPxADD.
EQUATION 25-1:
C specification (which applies to rates greater than
BRG Down Counter
SSPxADD<7:0>
BRG Value
0Ch
13h
19h
4Fh
09h
27h
09h
F
CLOCK
demonstrates clock rates based on
=
-------------------------------------------------
2011 Microchip Technology Inc.
SSPxADD
F
OSC
(2 Rollovers of BRG)
/2
F
OSC
400 kHz
400 kHz
308 kHz
100 kHz
308 kHz
100 kHz
100 kHz
F
+
CLOCK
1
4
(1)
(1)
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