PIC16LF1826-I/ML Microchip Technology Inc., PIC16LF1826-I/ML Datasheet - Page 180

• Manufacturer Part Number: PIC16LF1826-I/ML
• Description: 3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, n
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16LF1826-I/ML

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin QFN
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16(L)F1826/27
21.6.2
The Timer1 gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
TABLE 21-4:
21.6.2.1
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
21.6.2.2
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
21.6.2.3
The output resulting from a Comparator 1 operation can
be selected as a source for Timer1 gate control. The
Comparator
synchronized to the Timer1 clock or left asynchronous.
For more information see
Output
21.6.2.4
The output resulting from a Comparator 2 operation
can be selected as a source for Timer1 gate control.
The Comparator 2 output (SYNCC2OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information see
Output
DS41391D-page 180
T1GSS
00
01
10
11
Synchronization”.
Synchronization”.
Timer1 Gate Pin
Overflow of Timer0
(TMR0 increments from FFh to 00h)
Comparator 1 Output SYNCC1OUT
(optionally Timer1 synchronized output)
Comparator 2 Output SYNCC2OUT
(optionally Timer1 synchronized output)
TIMER1 GATE SOURCE
SELECTION
T1G Pin Gate Operation
Timer0 Overflow Gate Operation
Comparator C1 Gate Operation
Comparator C2 Gate Operation
1
TIMER1 GATE SOURCES
output
Timer1 Gate Source
Section 19.4.1 “Comparator
Section 19.4.1 “Comparator
(SYNCC1OUT)
can
be
21.6.3
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
21.6.4
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the
T1GGO/DONE bit will automatically be cleared. No other
gate events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See
Figure 21-5
If the Single Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See
details.
21.6.5
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
21.6.6
When Timer1 Gate Event Interrupt is enabled, it is pos-
sible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
Note:
TIMER1 GATE TOGGLE MODE
Figure 21-4
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
TIMER1 GATE SINGLE-PULSE
MODE
TIMER1 GATE VALUE STATUS
TIMER1 GATE EVENT INTERRUPT
for timing details.
 2011 Microchip Technology Inc.
for timing details.
Figure 21-6
for timing