PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 89

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.0
10.1
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The SSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI™)
• Inter-Integrated Circuit (I
An overview of I
tion on the SSP module can be found in the “PICmicro
Mid-Range
(DS33023).
Refer to Application Note AN578, “Use of the SSP
Module in the I
(DS00578).
 2005 Microchip Technology Inc.
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
SSP Module Overview
MCU
2
C operations and additional informa-
2
C™ Multi-Master Environment”
Family
2
C™)
Reference
Manual”
®
10.2
This
operational characteristics of the SPI module.
SPI mode allows 8 bits of data to be synchronously
transmitted
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and the SSPSTAT register (SSPSTAT<7:6>). These
control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Clock Edge (output data on rising/falling
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
edge of SCK)
Note:
section
SPI Mode
Before enabling the module in SPI Slave
mode, the state of the clock line (SCK)
must match the polarity selected for the
Idle state. The clock line can be observed
by reading the SCK pin. The polarity of the
Idle state is determined by the CKP bit
(SSPCON<4>).
and
contains
received
PIC16F87/88
register
RB2/SDO/RX/DT
RB1/SDI/SDA
RB4/SCK/SCL
RB5/SS/TX/CK
simultaneously.
DS30487C-page 87
definitions
and
To