PIC16F1827-I/ML Microchip Technology Inc., PIC16F1827-I/ML Datasheet - Page 159
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PIC16F1827-I/ML
Manufacturer Part Number
PIC16F1827-I/ML
Description
28 QFN 6x6mm TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16F1827-I/ML
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
CAN/I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin QFN
Programmable Memory
7K Bytes
Ram Size
384 Bytes
Speed
32 MHz
Timers
4-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Standby Current (pic16lf182x)
30 nA @ 1.8 V, Typical
Lead Free Status / Rohs Status
RoHS Compliant part
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TABLE 18-1:
REGISTER 18-1:
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
SRCLK
R/W-0/0
SRLEN
111
110
101
100
011
010
001
000
Set only, always reads back ‘0’.
SRLEN: SR Latch Enable bit
1 = SR Latch is enabled
0 = SR Latch is disabled
SRCLK<2:0>: SR Latch Clock Divider bits
000 = Generates a 1 F
001 = Generates a 1 F
010 = Generates a 1 F
011 = Generates a 1 F
100 = Generates a 1 F
101 = Generates a 1 F
110 = Generates a 1 F
111 = Generates a 1 F
SRQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
If SRLEN = 0:
SR Latch is disabled
SRNQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
If SRLEN = 0:
SRPS: Pulse Set Input of the SR Latch bit
1 = Pulse set input for 1 Q-clock period
0 = No effect on set input.
SRPR: Pulse Reset Input of the SR Latch bit
1 = Pulse reset input for 1 Q-clock period
0 = No effect on reset input.
Divider
SRCLK FREQUENCY TABLE
512
256
128
R/W-0/0
64
32
16
8
4
1 = Q is present on the SRQ pin
0 = External Q output is disabled
1 = Q is present on the SRnQ pin
0 = External Q output is disabled
SR Latch is disabled
SRCON0: SR LATCH CONTROL 0 REGISTER
F
OSC
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
SRCLK<2:0>
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
2 MHz
4 MHz
8 MHz
R/W-0/0
= 32 MHz
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
wide pulse every 4th F
wide pulse every 8th F
wide pulse every 16th F
wide pulse every 32nd F
wide pulse every 64th F
wide pulse every 128th F
wide pulse every 256th F
wide pulse every 512th F
F
OSC
R/W-0/0
1.25 MHz
39.0 kHz
78.1 kHz
2.5 MHz
156 kHz
313 kHz
625 kHz
5 MHz
= 20 MHz
(1)
(1)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit is set only
R/W-0/0
SRQEN
OSC
OSC
OSC
OSC
F
OSC
OSC
OSC
OSC
OSC
cycle clock
cycle clock
31.3 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
cycle clock
cycle clock
1 MHz
2 MHz
4 MHz
cycle clock
cycle clock
cycle clock
cycle clock
= 16 MHz
PIC16(L)F1826/27
SRNQEN
R/W-0/0
F
OSC
31.25 kHz
7.81 kHz
15.6 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
= 4 MHz
R/S-0/0
SRPS
DS41391D-page 159
F
OSC
1.95 kHz
3.90 kHz
7.81 kHz
15.6 kHz
31.3 kHz
62.5 kHz
125 kHz
250 kHz
R/S-0/0
SRPR
= 1 MHz
bit 0
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