PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 157

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.4
The MSSP module in I
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCLx) – RC3/SCK1/SCL1 or
• Serial data (SDAx) – RC4/SDI1/SDA1 or
The user must configure these pins as inputs by setting
the TRISC<4:3> or TRISD<1:0> bits.
FIGURE 15-7:
© 2006 Microchip Technology Inc.
Note: Only port I/O names are used in this diagram for
RD0/PSP0/SCK2/SCL2
RD1/PSP1/SDI2/SDA2
RC3 or
RC4 or
RD0
RD1
the sake of brevity. Refer to the text for a full list
of multiplexed functions.
I
2
C Mode
Read
Shift
Clock
MSb
SSPxADD reg
Stop bit Detect
Match Detect
MSSP BLOCK DIAGRAM
(I
SSPxBUF reg
SSPxSR reg
2
2
Start and
C mode fully implements all
C™ MODE)
LSb
Write
Set, Reset
S, P bits
(SSPxSTAT reg)
Addr Match
Internal
Data Bus
Preliminary
PIC18F45J10 FAMILY
15.4.1
The MSSP module has six registers for I
These are:
• MSSP Control Register 1 (SSPxCON1)
• MSSP Control Register 2 (SSPxCON2)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
• MSSP Shift Register (SSPxSR) – Not directly
• MSSP Address Register (SSPxADD)
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I
SSPxCON1 and SSPxCON2 registers are readable and
writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper 2 bits of the SSPxSTAT are
read/write.
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
SSPxADD register holds the slave device address
when the MSSP is configured in I
When the MSSP is configured in Master mode, the
lower seven bits of SSPxADD act as the Baud Rate
Generator reload value.
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
(SSPxBUF)
accessible
transmission,
REGISTERS
the
2
C mode operation. The
SSPxBUF
DS39682B-page 155
2
C Slave mode.
2
C operation.
is
not